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Abstract
An ultra-narrow 40-nm slotted waveguide is fabricated to enable highly efficient, electro-optic polymer modulators. Our measurement results indicate that VπL’s below ∼ 1.19 V.mm are possible for the balanced Mach-Zehnder modulators using this ultra-narrow slotted waveguide on a hybrid silicon-organic hybrid platform. Our simulations suggest that VπL’s can be further reduced to ∼ 0.35 V.mm if appropriate doping is utilized. In addition to adapting standard recipes, we developed two novel fabrication processes to achieve miniaturized devices with high modulation sensitivity. To boost compactness and decrease the overall footprint, we use a fabrication approach based on air bridge interconnects on thick, thermally-reflowed, MaN 2410 E-beam resist protected by an alumina layer. To overcome the challenges of high currents and imperfect infiltration of polymers into ultra-narrow slots, we use a carefully designed, atomically-thin layer of TiO2 as a carrier barrier to enhance the efficiency of our electro-optic polymers. The anticipated increase in total capacitance due to the TiO2 layer is negligible. Applying our TiO2 surface treatment to the ultra-narrow slot allows us to obtain an improved index change efficiency (∂n/∂V) of ∼ 22% for a 5 nm TiO2 layer. Furthermore, compared to non-optimized cases, our peak measured current during poling is reduced by a factor of ∼ 3.
© 2022 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
Integrated photonic devices have received significant attention during the last decade due to their compatibility with high volume manufacturing, low power consumption, small footprints, and large optical bandwidths. To meet the demand for ultra-high-speed optical modulation, versatile structures have been studied for optical modulators as crucial building blocks in various photonic systems, including microwave links [1], optical interconnects [2–4], and optical frequency comb generators [5]. Advanced modulators, such as ones based on the plasma dispersion effect [6,7] and the electro-absorption effect [8] have been the subject of much recent research due to their promising characteristics. Nevertheless, they are not free of challenges since the maximum frequencies of both types of modulators are limited by their capacitance [9].
Possessing impressive characteristics, including high switching speeds, high energy efficiency, and low drive voltages [10–13] as compared with other technologies, EOP-based modulators (EOP: electro-optic polymer) offer a highly-resilient-to-radiation and CMOS-compatible alternative for next-generation on-chip optical signal processing systems [14]. Although EOPs are typically prone to high temperatures in existing nanofabrication steps, they can be added later as a post-processing step. Polymer-assisted modulators have emerged in various formats, including single-mode strip waveguides [11,15–17], line-defect photonic crystal (PC) waveguides [18,19], polymer-based waveguides [20,21], slotted waveguides [22], and metal-polymer-silicon (Si) waveguides [23]. In all these structures, the goal is to maximize the field confinement to take full advantage of the phase shifts induced by either Pockels effect (i.e., $\mathrm {\chi }^2$) polymers [24–26] or nonlinear Kerr-effect (i.e., $\mathrm {\chi }^3$) polymers. Two widely-used structures are Si-organic hybrid (SOH) and plasmonic-organic hybrid (POH) using which modulators with high bandwidths (> 100 GHz) [12,13] and ultra-high modulation efficiencies [10,27–29] have been fabricated so far.
While plasmonic structures possess better optical field confinement (i.e., optical field confinement and propagation happen at the metallic surface), SOH devices offer a lower loss and CMOS foundry-compatible solution. When making EOP-based modulators using conventional Si strip waveguides, the EOP typically covers the waveguide. Only the evanescent field experiences the effective index change due to the polymer’s electro-optic (EO) effect [30]. Because of the large refractive index contrast between Si and EOP ($n_{\text {Si}}$ $\approx$ 3.42 vs $n_{\text {EOP}}$ $\approx$ 1.68), this type of SOH modulator suffers from poor optical field overlap for conventional Si strip waveguides. A low-loss solution can be implemented by all-polymeric structures in which the waveguide core is made of polymer (instead of silicon) using direct laser writing [31] or ultraviolet imprinting technology [32]. An EOP cladding will later spin coat on top of the formed polymer core. In addition to its low modulation efficiency, the compatibility of this approach with the existing CMOS foundry process is questionable. It has been proposed to use nano-slot Si waveguides in SOH structures to improve the modulation efficiency. Vertical slots with various slot widths from 75 nm to 210 nm have been theoretically and experimentally demonstrated to enhance the transverse electric (TE) mode intensity inside the Si nano-slots [33]. In polymer-filled slots, the field overlap can be tailored to provide large EO effects allowing one to make highly efficient modulators.
In slotted waveguides, narrowing the slot results in a better field overlap and, hence, a better modulation efficiency. Nevertheless, narrow slots suffer various challenges, including relatively complex fabrication as well as poor infiltration and poling. Authors in [34] demonstrated the reasons for EO coefficient reduction compared to its bulk material values as slot width ($W_\text {slot}$) decreases. They reported EO coefficients of polymers, and hence the benefits of a small slot start to diminish (slightly for $W_\text {slot}$<80 nm and drastically for $W_\text {slot}$<35 nm.) The infiltration and poling issues deteriorate the in-device EO coefficient (i.e. $r_{\text {33,in-device}}$), a crucial metric for the performance of a Mach-Zehnder modulator (MZM), and hence the overall modulation efficiency [33]. Indeed, the high leakage current during poling degrades the poling process. The maximum tolerable polling field before breakdown is limited due to the high leakage current. The authors in [35] argued that defects, including air gaps and impurities formed inside EOP material, can lead to local conductivity fluctuations, resulting in current hot spots that induce breakdown. The polling efficiency of EOP has been widely investigated in previous works. [36–40]. To overcome these issues, wider slots (up to 320 nm [19]) have been employed in conjunction with PC-slotted waveguides. However, design complexity and limited bandwidth are two challenges of this category of devices. Researchers in [35] have proposed the deposition of thin Alumina (Al2O$_3$) as an interface between EOP and Si or ITO (indium tin oxide) substrates. However, this study is also limited to bulk layers of the EOP material and has not been tested for slotted waveguides/modulators. Surface passivation advantages have also been studied elsewhere [41], where the authors investigated the effect of the titanium dioxide (TiO2) layer deposited by various techniques on reducing pedestal and finger resistivity. However, they did not explicitly discuss the leakage current dependency on the added TiO2 layer. We show such a thin layer of TiO2 can have even more significant benefits as a buffer layer inside slots, specifically for the EOP modulators featuring narrow slots.
This paper presents our approach for a hybrid Si-organic platform that uses EOPs in ultra-narrow slotted waveguides to achieve high modulation efficiencies. We report a series of surface preparations using a thin layer of TiO2 and infiltration techniques specifically for narrow vertical slots. We show that our approaches can improve the breakdown poling field and $r_{\text {33,in-device}}$. Section 2 describes the design criteria to obtain various performance metrics as functions of structural factors. Section 3 presents fabrication details for implementing air bridge interconnects to minimize the device footprints. We also demonstrate near-perfect void-free infiltration to decrease the poling current inside a 40 nm-wide Si slot. Section 4 presents a discussion of the simulation and experimental results. Section 5 will provide a conclusion.
2. Design details
SOH-based slotted modulators typically suffer poor Si-organic interfaces causing incomplete infiltration and inefficient poling [42]. Ideally, we need to establish a strong DC electric field (i.e., a poling field) inside the polymer without any DC current. Indeed, the leakage current flows between the sidewalls (i.e., between the cathode and the anode), preventing the complete poling of the chromophore molecules and may cause permanent damage/degradation to the polymer. While there is no standard recipe for surface functionalization, we have developed a customized surface treatment based on atomic layer deposition (ALD) of 5 and 10 nm of TiO2 that allows us to maintain large electric fields (100 V/$\mu$m) inside the slots for efficient poling and to avoid the breakdown field of the EOP. This method also helps polymer infiltration by blocking air bubble formation at slot sidewalls due to better sidewall adhesion [37,38,43–46].
The SOH-based slotted waveguide used for our MZM featuring the mentioned TiO2 layer is depicted in Fig. 1. Among the many performance metrics for an MZM, the modulator sensitivity ($S_{\text {p}}$, the effective mode index change versus the applied voltage) is one of the essential properties and is given by
Fig. 1. (a) 3D Schematic of the SOH platform used to build the asymmetric MZM. (b) cross-section of the device indicating the enhancing TiO2 layer. (c) normalized, applied electric field (poling DC/RF) distribution. $R_{\text {1}}$, $R_{\text {3}}$ represent the resistances of the two pedestals. $R_{\text {2}}$ and $C_{\text {tot}}$ represent the combined resistance and capacitance of the Si rails, EOP, and TiO2 layers, respectively.
Table 1 summarizes the modelling parameters and device geometries that we have used. One needs to evaluate the effect of the TiO2 layer on the modulator bandwidth. The capacitance of the thin TiO2 and EOP layers are found to be $C_{\text {TiO}_{2}}\approx ~$19 $p$F and $C_\text {EOP}\approx ~$0.078 $p$F by approximating the slot as a parallel plane capacitance. Here, we neglect the direct capacitance between two rails, i.e., the outer edge of the slot. The total equivalent slot capacitance is dominated by that of the EOP layer since the contribution of the TiO2 layer in series with the EOP layer is minimal ($C_\text {total}^{-1}$ = $C_\text {EOP}^{-1}+2{\times }C_{\text {TiO}_{2}}^{-1}\;\approx \;77.36\;f$F). On the other hand, the thin TiO2 layer does not contribute to the total resistance. Indeed, as reported in [21], adding TiO2 may even reduce surface charges and, hence, reduce the pedestal resistance by functionalizing it; this would also help improve the bandwidth of the device. The added TiO2 can slightly influence the voltage drop across the slot estimated by
Table 1. Device geometries and modelling parameters of the slotted-waveguide MZM
We have simulated the effect of the TiO2 thickness, among other factors, to see how it impacts various aspects of the device performance. The maximum poling efficiency is only possible when two conditions are met simultaneously: 1) optimal field overlap between the poling (DC) field and the optical TE (modal) field is obtained; 2) uniform void-free infiltration of the polymer inside the slot is achieved. The field overlap can be calculated by [28,47,48]
Due to the electric field discontinuity at the slot interfaces, it is well-known that the TE electric field inside the slot (i.e., in the polymer infiltrated region) will be enhanced by $n_{\text {Si}}^2$/$n_{\text {EOP}}^2$ ($\approx$ 3.42$^2$/1.68$^2$ = 4.14 in our device) [22]. Assuming a fixed $d_{\text {slot}}$, this ratio will be decreased to $n_{\text {TiO}_2}^2$/$n_{\text {EOP}}^2$ ($\approx$ 2.61$^2$/1.68$^2$ = 2.41), i.e., by a factor of $n_{\text {Si}}^2$/$n_{\text {TiO}_2}^2$ $\approx$ 1.717, for a fixed effective slot width ($W_{\text {eff}}$). Finite-difference eigenmode (FDE) simulations by COMSOL are required to model the effect of the TiO2 layer on the modal field distribution, as shown in Fig. 2. For comparison, we have repeated the calculations for a 100 nm-wide slot and 10 nm TiO2. It should be noted that the field enhancement is a function of both slot width and TiO2 thicknesses. In other words, while the field intensity inside the slot is linearly enhanced by adding more TiO2 for the 100 nm slot, it follows a different direction and is somewhat more pronounced for the 40 nm slot. Figure 2 suggests the advantage of the 40 nm structures and the increased resulting modulation efficiency ($V_\mathrm {\pi }$L). It also implies that the TE field inside the 100 nm-wide slot is distributed less uniformly. More importantly, the average TE field is lower at the slotted waveguide‘s center where the infiltrated EOP presents. In addition to better adhesion between EOP and the slot sidewall, adding TiO2 smoothes out the TE field and improves the poling efficiency.
Fig. 2. Electric field norm of the slotted arm with and without a TiO2 interface for (top) 100 nm slot and (bottom) 40 nm slot width. $W_{\text {eff}}$ is the effective slot width considering the space taken by TiO2.
Figure 3 shows the simulation results for $\hat {E}_e$, calculated halfway up the rails (i.e., 125 nm above the BOX layer in Fig. 1(b)). Together with Fig. 2, one may identify two immediate effects of the added TiO2 layer: 1) the poling field (i.e. $E_{\text {e}}$) is enhanced by factors of 30% and 80% for 5 nm and 10 nm of TiO2 on each side of the 40 nm slot, respectively (that is important because the polymer requires a minimum poling field of 100 V/$\mu$m for effective chromophore alignment) and 2) the uniformity of the modal field (i.e. $\hat {E}$) throughout the slot could be improved, as shown in Fig. 2. The uniformity of $E_{\text {e}}$ was previously reported in [35], where the authors employed an interface layer of Al2O$_3$ to enhance poling-field uniformity, albeit for non-slotted waveguide modulators. Fig. 4(a) shows the modal field intensity measured at the midpoint of the slot, where the infiltration of the EOP is most efficient. The thicker the buffer layer, the higher the TE field intensity due to the thinner $W_{\text {eff}}$. Figure 4(b) illustrates the power confinement factor ($\kappa$) in the slot. Depositing more TiO2 into a smaller slot will result in less space for the EOP. Figures 4(c) shows a more intuitive figure of merit, $\kappa |\hat {E}_{\text {avg}}|$, where $|\hat {E}_{\text {avg}}|$ is the average value of $E_{\text {e}}$ within the slot. The thicker the TiO2 used, the higher the value of $\kappa |\hat {E}_{\text {avg}}|$. Yet, as shown in Fig. 4(d), $\Gamma$ is reduced by adding more oxide. It is worth noting that, while both are optical-electrical field overlap factors, $\Gamma$ is different than $\kappa |\hat {E}_{\text {avg}}|$, and it is the parameter that eventually defines the performance of the device.
Fig. 3. Normalized (to 1 V applied) electric field distribution inside slots of width (left) 100 nm and (right) 40 nm. Higher poling field along with better field tolerance due to carrier barrier behavior of the oxide interface result in higher $r_{\text {33,in-device}}$ and, hence, better modulation efficiency.
Fig. 4. Electrical (poling/RF) and optical field characteristics for slots with 100 nm and 40 nm widths: (a) Modal field intensity at the slot center; (b) Power confinement ratio inside the slot relative to the entire propagation medium ($\kappa$); (c) Power confinement ratio multiplied by the electric field, $\kappa |\hat {E}_{\text {avg}}|$; and (d) Field overlap integral, $\Gamma$.
3. Fabrication methods
3.1 Device
Due to fabrication challenges and poling issues of ultra-narrow (e.g., 40-nm slots), slots wider than 100 nm are commonly used in slotted-waveguide SOH modulators. Next, we describe those challenges and provide our detailed process flow steps. The modulator fabrication flow diagram is shown in Fig. 5. We begin with a 250 nm / 3 $\mu$m BOX SOI chip. The slotted waveguide was formed by E-beam lithography (EBL) and dry etching. A JEOL JBX-9300FS EBL System, with a resolution of 20 nm at 100 pA beam current, was utilized to create ultra-narrow slots. For the E-beam resist, our silicon slot was patterned using HSQ 6%, whereas MaN 2403 was used for our pedestals. To reduce the insertion loss, it is essential to use an etching process with a moderate etch rate and less physical etching to achieve a smooth sidewall, especially when making such small slots. A chlorine-based etch process was used in an inductively coupled plasma (ICP) etching system to succeed in this crucial step.
Doping concentrations are designed to reduce the pedestal‘s total resistance, which carries poling and modulation signals to the slot sidewalls. After forming the MZM, 150 $\mu$m x 150 $\mu$m contact pads are fabricated in a third EBL step, with ZEP as the E-beam resist. A Denton Explorer E-beam evaporation system is employed for metallization in which a titanium (Ti) layer (10 nm) followed by a copper (Cu) layer (250 nm) is deposited under moderate vacuum conditions (pressure < $3 \times 10^{-6}$ Torr). The metal lift-off is processed using 1165 at 80 $^{\circ }$C overnight for gentle, crack-free interconnects. Then the polymer is prepared and spin-coated according to our recipe (discussed later). The EOP on top of the contacts, formed in the last step, is removed at an elevated temperature (> 130 $^{\circ }$C) before poling. Additionally, we investigated the usage of tunable directional couplers instead of the more common multimode interferometer (MMI) couplers or Y-splitters because they allow balancing the MZM to maximize the extinction ratio (data not shown here). The 100 nm gap of the directional coupler is protected by an additional layer of flowable oxide (FOx), which otherwise could be filled with the polymer during the EOP-deposition process.
To enable contacts for applying electrical signals (both RF and poling), vertical vias made of conducting materials, e.g., tungsten, are usually employed on top of the samples [16] and insulated with SiO2. However, the oxide cladding is not always an available fabrication option. In such a case, achieving metallic contact with the inner parts of the MZM is a challenge due to geometry limitations and the demand for the optimum device footprints. Compared to conventional vias, we also found that polymer infiltration could be more efficient using our air bridge-over-photonic-waveguide interconnect approach. This process, shown in Fig. 6, starts by spin-coating a 1.3 $\mu$m-thick E-beam resist (MaN 2410) on top of the already formed MZM. One should minimize the electrical resistance of the air bridge, which directly affects the poling efficiency and the device bandwidth. This critical characteristic is achieved by a reflow process in which the sharp corners of the processed rectangles are reduced from $\sim$ 90$^{\circ }$ to $\sim$ 70$^{\circ }$. We have determined that reflowing for 2 minutes at $\sim$ 145 $^{\circ }$C generates the best outcome. Employing the FDTD simulations, we have chosen the geometry requirements of the air bridge for minimal optical loss. Accordingly, our simulations show that minimum distances of $\sim$ 450 nm from the top of the waveguide/slot region and 600 nm from each side of the waveguide are necessary to avoid considerable optical loss caused by the air bridge. Next, an atomically thin alumina layer is coated using ALD, followed by one further step of E-beam lithography, copper sputtering and subsequent lift-off using Polymethyl methacrylate (PMMA) for metallization. Despite its nanoscale size, our developed process flow resulted in both mechanically stable and reproducible results for the air bridge. Depicted in Fig. 7 is the scanning electron microscopy (SEM) along with a microscopic image of the fabricated air bridge on top of the MZM.
Fig. 6. Fabrication steps for the air bridge interconnect include EBL, re-flow, metallization and ALD steps (cross-section and top views are shown for each step). PMMA and Ma-N 2410 E-beam resists are used as the metallization mask and bridge support, respectively.
Fig. 7. (a) SEM image of the fabricated air bridge after metallization and the removal of the MaN 2410. (b) microscope image of the fabrication asymmetric MZM (40 nm slot, 0.5 mm arm length) along with a zoomed view of the air bridge crossing the modulating arm.
3.2 Material
The most challenging step in making narrow-slot, EOP-filled waveguides is achieving void-free EOP infiltration of the slots [35,36,41]. In addition to the benefits mentioned previously, our TiO2 surface treatment can help in this regard. We have tested various mechanisms to enhance the polymer-Si interface. First, we ran a customized oxygen plasma cleaning step on the surface (using advanced vacuum reactive ion etching (RIE)). Excessive plasma cleaning, however, damages the waveguides and should be avoided. As illustrated in Fig. 8, we deposited a thin layer (5 nm) of TiO2 everywhere, including inside the slot, using a Cambridge ALD system. ALD is known to be the most precise deposition method for thin oxide films with desired thicknesses. ALD also produces a high-quality interface between the Si slot sidewalls and the oxide (TiO2), compared to alternative methods such as plasma-enhanced chemical vapour deposition (PECVD), and is known to provide conformal coatings even in confined spaces such as under our air bridges. The ALD process temperature was set to 150 $^{\circ }$C, and a layer of $\sim$ 0.7 Å was deposited in each cycle. The pulse and purge times in one ALD cycle were carefully monitored to maintain the quality of the oxide coating.
Fig. 8. Perspective view of a schematic of the slotted waveguide cross-section. Shown in red is the deposited 5 nm TiO2 layer (a zoomed view is shown on the left). The TiO2 layer coated on the Si rails and pedestals is not shown here.
Compared to the standard recipe for SEO125B (6.72% by weight according to Soluxra Inc.), we deliberately diluted the solution by increasing the volume ratio of the solvent (Dibromomethane) to SEO125B by a factor of $\sim$ 1.5. We have also devised a "rotating bubble" method for spin coating the EOP to replace the conventional "dropping" method prescribed by the manufacturer. In this method, we apply an appropriate amount of pressure to the dispensing pipette’s bulb to control the small bubble of 2$\sim$3 mm diameter formed at the end of the pipette. By moving the pipette, the bubble can be "pulled" across the surface of the chip to deposit a thin layer of the polymer (a few hundred nanometers thick). Simply dropping the EOP onto the chip’s surface leaves a bulky polymer that causes an additional loss, complicates accessing the contact pads and causes the EOP to develop harmful cracks. Using our optimized process, we have successfully developed a recipe for the spin coating that decreases the thickness of the EOP on top of the sample from > 3 $\mu$m to $\sim$ 450 nm. During the spin-coating process, due to the viscosity of the EOP, the initial drop, does not spread significantly. Still, the thin layer formed by our technique flows enough to increase the uniformity of the EOP across the critical portions of the chip. The thickness obtained is adequate since the waveguide height is only 250 nm. Our techniques for EOP dilution and coating also help decrease the additional loss imposed on the input/output grating couplers by the polymer. Consequently, as demonstrated later, this should result in better extinction ratios (ER), determined by the two arms' optical loss asymmetry. Another benefit of our EOP deposition approach is the infiltration inside the slot. By waiting a few minutes after spinning, we allow the polymer to be pulled into the slot by the capillary effect. Otherwise, the polymer may not penetrate the slot uniformly. We have obtained better polymer infiltrations by employing these techniques compared to non-optimized alternatives [35,36,41].
The coated sample is heated overnight in a vacuum oven at $\sim$ 75 $^{\circ }$C to remove leftover air gaps/voids from the slot. Figure 9 shows SEM images of the slot with and without the enhanced polymer infiltration method. The effect of an additive layer of alumina (Al2O$_3$) on the non-slotted waveguide [35] has been previously studied in [35]. For comparison, we have also deposited 5 nm of Al2O$_3$ and monitored the infiltration/adhesion of EOP into the slot/Si sidewalls [49]. Figure 9 demonstrates the improvement obtained for the TiO2/SEO125B interface compared to that of Al2O$_3$/SEO125B. As seen in Fig. 9(b), almost-perfect infiltration of the EOP is achieved for the TiO2 deposited sample, whereas the infiltration of the slot with Al2O$_3$ walls is not void-free. Both samples were fabricated using identical processes except for the material employed as the buffer layer. Comparison of $V_\mathrm {\pi }$L along with SEM images can be a more conclusive way to judge the level of infiltration.
Fig. 9. (a) A false-colored SEM of a 100 nm slotted waveguide, with 5 nm TiO2, infiltrated with SEO125B. (b) A magnified image of the slot shown in (a) demonstrates the excellent infiltration and surface adhesion. (c) SEM of a 100 nm slotted waveguide with an ALD-deposited, 5 nm thick, Al2O$_3$ layer, as was done in [49].
4. Results and discussion
The linear EO effect (i.e. the Pockels effect) can be induced in the EOP by orienting its chromophore molecules so that the optical center of symmetry of the polymer is removed [50]. Generally speaking, the larger the poling field inside the slot, the more significant the induced EO effect. However, the maximum poling field is limited by the polymer breakdown. SEO125B has a standard poling recipe in which a poling field of at least 100 V/$\mu$m should be applied to the polymer. To obtain this field, we minimize the resistance of the 50 nm pedestal and the waveguide rail compared to the thin-film EOP. Then, a temperature ramp of 10 $^{\circ }$C/min is applied while maintaining the field to reach a state where chromophores can be readily aligned. The temperature is increased from 80 $^{\circ }$C to 150 $^{\circ }$C, given that the polymer‘s glass transition temperature, $T_\text {g}$, is $\sim$ 145 $^{\circ }$C. The applied current drawn is recorded throughout this process. Figure 10(a) depicts the cold resistance, while Fig. 10(b) shows the measured current versus the temperature ramp used during the poling procedure for a 40 (nm) slotted waveguide with and without the TiO2 layer.
Fig. 10. (a) Cold (i.e., room temperature) resistance measurements and (b) the measured current versus time for the temperature ramp used during the poling procedure. Less than one-third of the peak measured current is observed when the thin TiO2 protection layer is applied.
Our TiO2 surface functionalization results in a peak current, less than one-third of that in the non-treated surface case. Considering a surface area of $250\times 10^{-9}\times 3\times 10^{-3}$ m$^2$, the peak current of 206 nA observed for the TiO2-protected case (Fig. 10(b)) is equivalent to a current density of $\approx$ 275 A/m$^2$. This number is within the range reported in [33], albeit the authors reported results for a 75 nm slot size. Since our device has a 40 nm slot, it is anticipated that a higher $S_{\text {p}}$, and hence modulation gain, should be achieved. We believe this improvement is due to the thin TiO2 layer acting as a "carrier barrier" and our improved EOP infiltration. In other words, the high $r_{33,\text {in-device}}$ reported in [33] (associated with the higher optical field overlap thanks to PC-based structure) could be even more enhanced using our proposed TiO2 addition layer. An unexpected observation from Fig. 10(b) is the occurrence of the maximum poling current at lower temperatures than $T_\text {max}$. Such unexpected variations of the poling current with the temperature have been observed earlier [40,45], although no clear physical mechanism has been suggested. We feel that the small size of the slot and the low EOP volume in the platform can be contributing factors. Nevertheless, a careful and detailed study of this phenomenon is needed to provide a convincing explanation.
Figure 11 displays the shift in the transmission of the MZM as a function of the applied voltage. A detuning efficiency of 120 pm/V with a free spectral range (FSR) of $\sim$ 1.15 nm is observed, which translates to a modulation efficiency of $\sim$ 2.396 V.mm for our asymmetric MZM (or $\sim$ 1.19 V.mm in push-pull configuration). Similar to what we demonstrated in [49], a linear transfer function for achieving a $\pi$ shift is expected. The large ER > 20 dB is due to our directional couplers instead of the more conventional Y-junctions or MMI couplers. Simulation results shown in Figs. 12(a) and 12(b), predict $\partial n / \partial V$ (and hence $V_\mathrm {\pi }$L) versus TiO2 changes in different directions, depending on the slot width. Indeed, the TiO2 protection layer results in larger possible poling fields with lower currents and hence better chromophore orientation, i.e., enhanced poling efficiency. To obtain the range of slot widths in which the performance is boosted by adding TiO2, we study $r_{33,\text {in-device}}$, shown in Fig. 13. Rewriting Eq. (1), this factor is calculated by
Fig. 11. Transmission spectra of a slotted, SOH MZM with a TiO2 passivated surface, a 40 nm slot width, and a 0.5 mm arm length.
Fig. 12. (a) Modulation efficiency ($V_\mathrm {\pi }$L) and (b) effective mode index changes versus the applied voltage ($S_{\text {p}}$) as functions of TiO2 thickness for devices with 100 nm and 40 nm slot widths.
Fig. 13. The (a) field overlap integral ($\Gamma$), (b) modulation efficiency ($V_\mathrm {\pi }$L), (c) $r_{\text {33,in-device}}$, and (d) modulation sensitivity ($S_{\text {p}}$), all versus the slot width. Better performance is achieved by using a smaller slot, our TiO2 surface treatment, or a combination of both.
The benefits of using an ultra-narrow slot (i.e. 40-70 nm) are evident in Fig. 13 in which $\Gamma$, $r_{\text {33,in-device}}$, $S_{\text {p}}$ and $V_\mathrm {\pi }$L are predicted. The yellow band indicates this region. In these estimations, we used the maximum value of $r_{33} \sim$ 100 pm/v for TiO2-added devices (with close-to-perfect EOP infiltration), whereas a correction factor of $\sim$ 0.77 was applied to the case of devices with no TiO2 layer. This factor is based on our previous work in [49], where a $V_\mathrm {\pi }$L $\sim$ 3.125 V.mm was reported for the same MZM structure without TiO2 compared to $\sim$ 1.19 V.mm shown in this work. While Fig. 13(a) predicts smaller $\Gamma$ for no-TiO2 cases, our surface treatment can yield higher $S_{\text {p}}$, lower $V_\mathrm {\pi }$L, and, hence, higher $r_{\text {33,in-device}}$. Since the modulator's gain is directly proportional to $S_{\text {p}}$, smaller slots can simultaneously result in higher modulator gains when appropriate TiO2 layers are employed. Another advantage of our oxide surface treatment is that it can result in higher modulation sensitivity for smaller (and hence more challenging, fabrication-wise) slot widths because of better poling (represented by $r_{\text {33,in-device}}$). In other words, instead of fabricating a 40 nm slot, one can use a 50 nm one and add 5 nm TiO2 to obtain the same level of field enhancement. Ultra-narrow slots also suffer higher optical loss and inhomogeneous field distribution [34] associated with sidewall roughness. Additional benefits of the added TiO2 layer on the mentioned characteristics demand further studies.
In this work, we primarily focused on poling and infiltration efficiency. However, our simulations (using COMSOL Multiphysics) shown in Fig. 13(b) anticipate that $V_\mathrm {\pi }$L can be further improved if appropriate doping is employed. For instance, a modulation efficiency of $\sim$ 0.35 V.mm should be achievable for 40 nm slot passivated with 5 nm TiO2, and doped uniformly with a concentration of $\sim 10^{18}~$cm$^{-3}$ for the pedestal (and rails) and $\sim 10^{20}~$cm$^{-3}$ for the electrical contacts. Accordingly, $R_1$ and $R_3$ in Fig. 1(c) decrease to $\sim$ 36 $\Omega$, resulting in less voltage drop across two pedestals and more across the slot. As investigated in [41], surface passivation with TiO2 results in enhanced conductivity of the pedestals, improving the poling efficiency and speed simultaneously. We ignored this additional benefit of the added TiO2. Despite the relatively large $C_{\text {tot}}\sim$ 77.36 $f$F caused by the ultra-narrow slot, a total $(R_1+R_3)C_{\text {tot}}\sim$ 5.57 $p$s is expected. We used a fixed value for $r_{\text {33}}$ in our simulations. Adding the effect of narrowing slot size on $r_{\text {33}}$ can be a potential direction for a future study. One may also need to estimate the effect of $R_{\text {bridge}}$ on the total R$\times$C and overall modulator bandwidth, which has been ignored in our simulations. Further studies are required to determine the effectiveness of alternate passivation materials, including Hafnium oxide (HfO2). In [51], the authors studied the effects of various charge barriers on the efficient poling of thin-film EOP materials. While their studies were focused on non-slotted structures, they found interesting results about further benefits of a Benzocyclobutene barrier layer over TiO2. However, the application of such a buffer layer inside ultra-narrow slots has yet to be surveyed.
5. Conclusion
An MZM implemented on the SOH platform was introduced in which we utilized the well-known advantages of slotted waveguides and the significant EO effects of polymers. Slot widths as small as 40 nm were fabricated to improve the modulation efficiency. To overcome the challenge posed by the high poling current, which adversely affects the modulation efficiency, we developed a series of fabrication steps to passivate the surface and improve EOP infiltration using atomically-thin layers of TiO2. Both FDTD and electrostatic simulations were employed to optimize the geometry of the surface-treated device. For narrow slots featuring TiO2 passivation layers, we demonstrated a factor 3 reduction in the poling current, a larger poling field, and a uniformly-distributed, highly-confined, in-slot modal (optical) field. As a result, we have achieved a larger $r_{\text {33,in-device}}$ compared to the case with no surface passivation. Also, our modified polymer spin-coating technique obtained almost perfect infiltration, with a very thin (< 450 nm) final EOP layer on top of the device. This study shows that the poling/RF field inside the 40 nm (100 nm) slot increases by $\sim$ 30% ($\sim$ 10%) when a carrier barrier layer of 5 nm of TiO2 is employed. In other words, without the oxide interface layer, the required poling voltage must be higher to obtain the minimum required field of 100 V/$\mu$m for the SEO125B polymer. As discussed in [35], this layer can increase the maximum tolerable field for the EOP beyond the moderate value of 100 V/$\mu$m, thus further increasing the modulation efficiency. Also, we have studied the modulator sensitivity is improved from $\sim$ 1.7 V$^{-1}$ to $\sim$ 2.07 V$^{-1}$ ($\sim$ 3.3 V$^{-1}$) for the 5 nm (10 nm) TiO2 layer inside our 40 nm slot-waveguide modulators. The lower drive voltages obtained in this paper can reduce transmittance noise figures.
To improve compactness, we have also developed fabrication steps to create air bridge interconnects to carry electrical signals instead of conventional vias. Despite their benefits, the proposed bridge deteriorates the RF performance of the modulator because of which optimizing the bridge seems necessary. Multiple air bridges are required to shrink the overall R${\times }$C time constant if a travelling wave electrode (TWE) is required. Nevertheless, the detailed fabrication steps described in this paper can be useful in microring modulators requiring one bridge. Further studies are required to determine the effectiveness of other alternative materials, including HfO2. Even though we have focused on the modulation efficiency, our simulations show R${\times }$C times constants as small as $\sim$ 5.57 $p$s and a modulation efficiency of $V_\mathrm {\pi }$L$\sim$ 0.35 V.mm should be simultaneously obtainable. The lower drive voltages made possible using our design approaches and our methods for fabricating ultra-narrow EOP-infiltrated slotted waveguides will also reduce transmittance noise figures for photonic integrated circuits. While it was not the focus of this paper, it can be proved that the proposed asymmetric MZM structure in this work is advantageous for implementing high gain modulators featuring small $V_\mathrm {\pi }$L. More specifically, while Si suffers free carrier absorption and two photonic absorption effects, building the second (non-modulating) arm using a low-loss material such as SiN can increase the overall gain. [49].
6. Author contributions
The main idea of the demonstrated slot modulators and all designs and fabrication processes were developed and implemented by I. T., A. A. E., and A. A at Georgi Tech. R. D., H. M., and T. F. participated in the fabrication process implemented by I. T., S. S., L. C., and N. A. F. J. and A. T. participated in the simulations. All authors contributed to the manuscript. All authors have approved the final version of the manuscript.
Funding
National Science Foundation (ECCS-1542174); Canada Foundation for Innovation; B.C. Knowledge Development; SiEPICfab; Natural Sciences and Engineering Research Council of Canada; Defense Advanced Research Projects Agency.
Acknowledgments
The work was supported by the Defense Advanced Research Project Agency (DARPA) through the DARPA MOABB project. It was performed in part at the Georgia Tech IEN, a member of the National Nanotechnology Coordinated Infrastructure (NNCI), supported by the National Science Foundation (ECCS-1542174). This research was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC), the SiEPICfab consortium (http://siepic.ca/fabrication), the B.C. Knowledge Development Fund (BCKDF) and the Canada Foundation for Innovation (CFI). Access to tools was facilitated by CMC Microsystems. The authors would like to thank Amir H. Hosseinnia for his valuable feedback for nanofabrication and his time in taking the SEM images. Also, the authors would like to thank Maryam Moridsadat for her helpful feedback regarding the simulation results.
Disclosures
The authors declare that there are no conflicts of interest related to this article.
Data Availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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