1. Introduction

Over the last few decades, global internet protocol traffic has been increasing and is expected to reach an annual run rate of 4.8 zettabytes by 2022, according to forecasts from CISCO [1]. Simultaneously, data centers have experienced an unprecedented exponential growth in data center traffic, leading to the rise of hyperscale data centers [2]. For higher spectral efficiency, a pulse amplitude modulation four level (PAM-4) format has been standardized in the IEEE 802.3 and 100 G Lambda Multi-Source Agreement (MSA) [3,4]. Bandwidth demands drive revolutionary changes in data center interconnection, and a high input/output (I/O) bandwidth density is accomplished by photonic integration. In particular, silicon photonics (SiPh) integration has emerged as one of the most promising technologies because it affords high density, high yield, low cost, and a small footprint owing to its compatibility with a well-established complementary metal-oxide-semiconductor (CMOS) process [5].

SiPh enables the integration of almost all types of transmit and receive components into a photonic integrated circuit (PIC) die. SiPh foundries have provided these devices as a device library contained in the process design kit (PDK) for rapid prototyping through multi-project wafer (MPW) services [6–10]. Compared with conventional optical sub assembly (OSA) technologies [11], SiPh integration can more significantly reduce the cost of individual devices, optical alignment, and testing required for manufacturing and packaging. Because of these advantages, many groups are attempting to commercialize SiPh-based transceivers. The current market is dominated by 100 G/lane transceivers [12–15]. The achievable bit rate per lane is determined by electro–optic bandwidth of the silicon modulator. Even though the foundries have released several PDK modulators with electro-optic bandwidth beyond 40 GHz, designing is still required for “application-specific” modulators, considering tradeoffs between performance metrics such as a modulation efficiency, insertion loss, and bandwidth [16]. Among the various modulators, Mach–Zehnder modulators (MZMs) have been successfully commercialized and widely deployed owing to their well-balanced performance metrics, spectral tolerance, and low complexity [6]. As an example, it has been demonstrated in a previous study that the MZM meets the MSA requirements for 400G-DR/FR4 applications based on the optimization of the PN-junction design [14].

With respect to the light sources, extensive research has been conducted to integrate III-V optical gain medium or laser into silicon die. These are categorized into wafer-level integration [17–19] and package-level integration [20–24]. Wafer-level integration is the direct bonding of InP dies to a silicon-on-insulator (SOI) wafer (called a heterogeneously integrated laser). The laser cavity is formed by two silicon waveguide reflectors (for example, Bragg reflectors). Thus, the heterogeneous integration affords the advantages of simplified packaging and low coupling loss below 0.5 dB [19]. However, it can be developed by only a few major integrated device manufacturers (IMDs) and is inaccessible to fabless players. As an alternative, CISCO has introduced a method of optical coupling of a distributed feedback (DFB) laser diode (LD) die to the SiPh die using a ball lens with coupling loss below 2 dB [23]. Without the assembly of ball lens, GlobalFoundries demonstrated butt-coupling between LD and SiPh dies via flip-chip bonding [24]. A silicon edge coupler (EC) with a typical inverse taper structure is required for efficient coupling. However, the best-in-class technologies such as immersion 193 nm lithography might be required to realize an extremely narrow tip of the EC with high reliability [25]. Moreover, there are no reports of flip-chip integrated lasers applied to 100 G/lane transceivers.

In this paper, we propose and demonstrate a fully-integrated SiPh transmitter (Tx) with a hybrid flip-chip bonded laser that enables operation at 106 Gb/s. We present a simple yet effective method for implementing a hybrid laser using a suspended EC. The suspended EC featured a suspended SiO₂ spot-size converter (SSC) [26]. Compared with the previous study [24], our hybrid laser exhibits several advantages, such as a larger misalignment tolerance, ease of flip-chip bonding, and usability of legacy 193 nm lithography. We describe the details of the proposed structure and report the results of the misalignment tolerance and butt-coupled optical power of the SiPh Tx die. We further explain the method for optimizing the design of an LD recess in the Tx die for successful flip-chip bonding.

Co-integrated into the Tx die, a silicon MZM accommodates a 53 GBd (Gbaud) PAM-4 signal. First, we address the design, RF characteristics, and eye performance of a stand-alone MZM. To combat the parasitic inductance of the Tx, we propose a structure in which high-density off-chip silicon capacitors (SCs) are populated onto the Tx die. To assess the impact of SCs, we experimentally evaluated the RF and eye performances of the MZM-integrated Tx with external light feeding. Subsequently, we implement the fully-integrated Tx with the hybrid flip-chip bonded laser and package the driver IC on the Tx board. Finally, we confirm the feasibility of the fully-integrated Tx by demonstrating 106 Gb/s real-time operation in conjunction with a commercial digital signal processing (DSP) chip.

The remainder of this paper is organized as follows: in Section 2, we present an overall architecture of the fully-integrated Tx; Section 3 details the structure and design of hybrid flip-chip integrated laser; Section 4 includes the design of stand-alone MZM and the measurement results; in Section 5, we assess the impact of the SCs on the MZM-integrated Tx and demonstrate the 106 Gb/s real-time operation with the fully-integrated Tx.

2. Overall architecture of proposed transmitter

A schematic of the fully-integrated 53 GBd PAM-4 SiPh Tx is illustrated in Fig. 1(a). The DFB LD with SSC is integrated into the recess (denoted as LD recess in Fig. 1(b)) of the Tx die via flip-chip bonding. Emitting continuous-wave (CW) light in the 1310 nm range, the LD in the recess was butt-coupled to the suspended EC (denoted as EC1). The EC consists of two sections of the SSC made of stacked oxide (SiO₂) layers formed in a tapered structure and a silicon inverse taper [26]. The SSC is designed to achieve optimum matching with the single mode fiber (SMF). As discussed later, this laser structure provides several advantages in terms of misalignment tolerance and a simple flip-chip bonding process. The coupled light in the silicon waveguide is sent to the differential-drive MZM for 53 GBd PAM-4 signal modulation. The MZM consists of a 1 × 2 multimode interference (MMI) coupler, 2 × 2 MMI coupler, and pair of PN-junction phase shifters (PN-PSs) and thermo–optic phase shifters (TOPSs). The MMI couplers featured ∼50:50 coupling ratio. Two germanium-based photodetectors (denoted as PD1 and PD2) monitor each tapped optical power from a corresponding 1 × 2 directional coupler with ∼90:10 coupling ratio. By adjusting the applied voltages of the TOPSs, the MZM is biased at the quadrature point where the converted photocurrents of PD1 and PD2 are equal. Propagating to the EC (EC2), the modulated optical signal is launched into a SMF.

 

Fig. 1. (a) Schematic of the 53 GBd PAM-4 SiPh Tx with the hybrid flip-chip integrated laser and driver IC packaged on the printed circuit board and (b) 3D schematic of the SiPh Tx die (SiPh: silicon photonics, Tx: transmitter, LD: laser diode, EC: edge coupler, MZM: Mach-Zehnder modulator, PN-PS: PN-junction phase shifter MMI: multimode interference, TOPS: thermo-optic phase shifter, PD: photodiode, SC: silicon capacitor, IC: integrated circuit, UBM: under bump metallization).

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The Tx die and driver IC die are placed side by side on a printed circuit board (PCB) and directly connected through wire bonds; this is also known as 2D integration. This approach is still applied in commercial 100 G/lane SiPh transceivers [12,13,15] while compromising between convenient packaging and issues of I/O density and parasitic inductances. Similar to the power-efficient drivers represented in [27–29], the driver IC requires output common mode voltages (${V_{OCM}}$) that should be supplied through the Tx die. The optimum ${V_{OCM}}$ was applied by adjusting the DC voltage at the far-end termination of the MZM (${V_{RT}})$. On-board and on-chip inductive lines including wire bonds are required for routing from a power supply on the PCB that degrades the RF performance [30]. To effectively decouple the parasitic inductance, we introduced an off-chip SC die (denoted as SC0) populated onto the Tx die. The SC should have a high-density feature for area efficiency. ${V_{OCM}}$ was applied to the MZM cathode. If the output ground pads of the driver IC were connected to the RF ground electrodes of the MZM, the PN-junction bias voltage (${V_{PNJ}}$) would be equal to ${V_{OCM}}$. However, their optimum values are generally different. An additional DC power supply was connected to the ground electrodes of the MZM (${V_{MZM}}$), thereby providing an adjustable PN-junction bias voltage, ${V_{PNJ}} = {V_{OCM}} - {V_{MZM}}$. As in the termination design, two SCs (denoted as SC1 and SC2) were added to the upper and lower RF ground electrodes, respectively.

Figure 1(b) shows a 3D schematic of the SiPh Tx die for the full integration. The Tx die is fabricated in a 200 mm SOI CMOS compatible process offered by Advanced Micro Foundry (AMF) via a dry 193 nm lithography process [6]. The SOI wafer features a top silicon layer with ∼220 nm thickness, a buried oxide (BOX) layer with ∼3 µm, and a silicon substrate with ∼725 µm. The foundry provides two types of trench processes: i) shallow trenches with solder bumps and under bump metallization (UBM) and ii) deep trenches. First, the recess patterns of the hybrid flip-chip integrated laser (denoted as LD recess in Fig. 1(b)) are defined by the shallow trench process. It is formed by etching away the top silicon layer (BOX) and partially etching the silicon substrate. The etching depth was ∼10 µm. The UBM and solder bumps were fabricated within the recess for mechanical support and electrical contact to inject current into the LD. Four pedestals are formed by the silicon waveguide layer (that is, top silicon layer) as vertical stops that ensure high alignment accuracy. As will be discussed later, the altitude of the optical mode of the flip-chip LD and suspended EC are automatically aligned, while dramatically reducing the challenges of the flip-chip bonding process. Second, recesses for sitting the SCs (denoted as SC recess in Fig. 1(b)) are formed by the dry- and wet-etching process (deep trench) with a depth of ∼120 µm. Horizontal SCs (that is, both electrode contacts on the top surface) were chosen for wire bonding to the pads of the Tx die. It should be noted that the same fabrication process as that of the suspended ECs and TOPSs is applicable for the deep trench; therefore, the fabrication complexity in not increased [31].

3. Hybrid flip-chip integrated laser

3.1 Structure

Figure 2(a) shows a schematic of the structure of the hybrid flip-chip integrated laser formed on a SiPh die. It consists of suspended EC, electrode contacts (that is, UBM and solders), and four pedestals in the recess. As mentioned earlier, suspended EC was adopted for laser-to-SiPh butt-coupling. The four pedestals are vertical stops (v-stops) for LD. The top surface of the v-stops was that of a bare silicon waveguide layer. V-stops are used to anchor the LD at the designed height during the flip-chip bonding process. We used the NeoPhotonics DFB LD that features an SSC for mode-size matching. The LD also has its own v-stop at the height of its mode center, as shown in Figs. 2(b) and 2(c). Because the vertical center of the optical mode of the suspended EC is at the center of the silicon waveguide layer, the vertical centers of the two modes of the LD and EC coincide automatically as the two vertical reference planes meet in the flip-chip bonding process. Thus, we need to consider only horizontal alignment that dramatically alleviates the challenges of flip-chip bonding. The use of v-stops is widely known, but there is no consensus on the location of the vertical reference plane [20,21]. The advantage of vertical reference at the top of the bare silicon waveguide layer (as in our design) is that it is easy to obtain a precise etching depth. Because the reference plane is the boundary between the silicon and cladding oxide, one can readily obtain a precise reference position by selective etching and employing end-point detection techniques.

 

Fig. 2. Schematic of (a) recess structure for the LD, (b) front view, and (c) side view of the hybrid flip-chip integrated laser (WG: waveguide, LD: laser diode, UBM: under bump metallization).

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For a recess with v-stops, there are three degrees of freedom: the x, z, and the angle of the LD waveguide relative to the EC in the xz-plane. The x, y, and z coordinates are shown in Fig. 2(a). Owing to the vertical reference plane, the misalignment in the y-direction and angular shift in the out-of-plane direction are extremely small. The shifts in the horizontal direction (x-direction) and in the forward/backward direction (z-direction) matter, whereas the angle is usually negligible in the flip-chip bonding process. Figure 3(a) shows the measured power penalty owing to the shifts. In the horizontal direction, the 1 dB-tolerance was 2.3 µm. This is considerably large, considering the 3-sigma placement accuracy of the recent advanced bonders that is ±1.0 µm (AMICRA, AFC Plus). In the vertical direction, the 1 dB-tolerance was 1.2 µm. Although this is considerably smaller than that in the horizontal direction, it is sufficiently large because the shift in the vertical direction is negligible thanks to the v-stops. In the z-direction, the loss increased by ∼1 dB per 10 µm, as shown in Fig. 3(b). This is an extremely dull dependence, considering the accuracy of the flip-chip bonders.

 

Fig. 3. Measured power penalty due to the misalignment of the LD from the suspended EC with (a) horizontal (in x-direction) and vertical (in y-direction) shift and (b) distance between the LD and the EC (in z-direction).

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3.2 Optimization of recess design by Monte–Carlo method

In the vertical design of the recess, we need to determine the parameters such as the depth of the recess and solder height. It is a simple arithmetic in principle, but the variation in the parameters complicates the problem. The variation according to location on a single wafer is empirically small and negligible, but the wafer to wafer variation causes the problems. If not appropriately designed, the LD electrodes may meet the UBM, whereas the vertical references of the LD and SiPh dies may not. This indicates bonding failure. At the other extreme, the LD electrode may not meet the solder top surface, leading to bonding failure. To reduce the probability of these failures, we employ Monte–Carlo methods to optimize the design parameters by considering parameter variation.

The four parameters related to vertical design are shown in Fig. 4(a). Each parameter has its design value ${x_0}$ and a limit of its deviation $\varDelta x$, while x is e, s, u, or t, where e, s, u, and t are electrode height of LD, solder height, UBM height, and recess depth, respectively. The deviation limits of these parameters were obtained from the LD vendor and SiPh foundry. We generated N samples of e, s, u, and t via random number generation. Because the distribution of each parameter and/or its 3-sigma deviation is not known, we assumed that it is constant for $|{x - {x_0}} |\le \varDelta x$. To determine the success or failure of bonding, we defined three more variables: $g = t - e - u$ is the gap between the UBM and LD electrodes after bonding;$\textrm{}d = s - g$ is the excess height of the solder; $r = s/g$ is the ratio of the solder height before bonding to that after bonding. If there is no loss of solder volume during the bonding process, r is the same as the ratio of the solder area after bonding to that before bonding. Three conditions for success were defined using the new variables: (a) $g \ge {g_{min}}$, (b)$\textrm{}d \ge {d_{min}}$, and (c)$\textrm{}r \le {r_{max}}$. (a) prevents the LD electrodes from touching the UBM. (b) indicates the presence of excess solder after bonding. This ensured the meeting of the LD electrodes and solders. (c) is required to prevent short-circuit owing to the overflow of the solder. We set ${g_{min}}$, ${d_{min}}$, and ${r_{max}}$ as 0.5 µm, 1.0 µm, and 4, respectively.

 

Fig. 4. (a) Parameters used in the calculation: e is the height of the LD electrode, s the solder height, u the UBM height, and t is the recess depth from the vertical reference plane, (b) success probability as a function of the designed recess depth in the fixed and adaptive solder scheme, and (c) adaptive solder height according to the measured recess depth.

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By imposing the three conditions on each sample, we can determine whether the sample is a success or a failure. We defined the success probability as $n/N$, where N is the total number of samples and n is the number of successful samples. To determine the solder height, we used two different strategies as follows: i) fixed solder height regardless of the implemented recess depth and ii) adaptive solder height. For the fixed solder height case, the success probability for given design depth ${t_0}$ and solder height ${s_0}$ is expressed as

To increase the probability of success, one may adapt the solder height to the measured recess depth after etching. For the adaptive solder height case, the success probability is expressed as

3.3 Flip-chip bonding implementation

We used an adaptive scheme and designed a recess depth of 10.0 µm as shown in Fig. 4(b). After etching the recess, the implemented recess depth is measured and the design value of the solder height is then determined, as shown in Fig. 4 (c). The solder process should be carried out with the target solder height across the whole wafer. Figure 5(a) shows an image of the LD flip-chip bonded to the implemented recess on the SiPh Tx die. This shows that the LD die was anchored vertically by v-stops. The silicon waveguide layer was left on top of the v-stop and served as the vertical reference. Figure 5(b) shows the optical power launched on the suspended EC estimated from the measured LI curves of the LD, assuming the coupling loss between the LD and the EC to be 6 dB that was measured separately. This shows that the optical power coupled to the silicon waveguide was greater than 10 dBm, with an applied current of 84 mA. In the measurement, the LD was bonded to a metal carrier with a thermally conductive epoxy adhesive. Meanwhile, in the case of flip-chip bonded LD, the heat generated in the LD is released to the silicon substrate through the solder bumps and UBM.

 

Fig. 5. (a) Scanning electron microscope (SEM) image of the implemented hybrid LD; (b) estimated optical power coupled with silicon waveguide as a function of the applied current.

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4. Stand-alone silicon modulator

4.1 DC and RF characterization

In this section, we address a stand-alone MZM to evaluate its own DC and RF performances. Its PN-PS is the same as the MZM to be integrated in the Tx die. As shown in Fig. 6(a), each arm of the MZM has a coplanar waveguide (CPW) transmission line in the Ground–Signal–Ground (GSG) configuration. The MZM is driven by a pair of GSGSG differential signals that affords the advantages of drive voltage distribution, inter-device crosstalk reduction, and ease of driver IC integration [32–34]. The CPW electrode features ∼10 µm signal trace width, ∼100 µm ground trace width, and ∼10 µm spacing. The center-to-center separation between the two signal traces was ∼260 µm. The total length of the transmission line was ∼2.5 mm and the total active length (that is, the total PN-junction length) was ∼2.1 mm. The MZM features a meandering optical waveguide structure for alternating-side PN-junction loading on the CPW electrode that consequently suppresses the undesired RF mode (that is, slot-line mode) [35]. The PN-PS is divided into ten segments, whose PN-junction waveguide features a length of 210 µm.

 

Fig. 6. (a) Microscope image of the stand-alone MZM, (b) schematic of cross-sectional design of the PN-junction segment, and (c) equivalent circuit model.

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Figure 6(b) illustrates the cross-sectional design of the PN-junction segment with the dimensions. The PN-junction segment was defined by a PN-doped rib waveguide with a width of ∼400 nm and a slab thickness of ∼90 nm. At the center of the rib waveguide, a lateral PN-junction geometry was formed with ∼6e17 cm^–3 p-dopants and ∼5e17 cm^–3 n-dopants. Intermediate P + and N + regions of ∼2e18 cm^–3 concentration were added to reduce the slab resistance (${R_{pn}}$). The ohmic contact regions were heavily doped with more than ∼1e20 cm^–3 p- and n-dopants, respectively. From the measured optical spectra of the MZM (at ∼1300 nm wavelength), ${V_\pi }{L_\pi }$ (at DC) of the PN-junction waveguide was 1.63, 1.74, and 1.77 V·cm at 1, 2, and 3 V reverse bias, respectively. The insertion loss of the MZM was measured to be 4.53, 4.36, 4.28, and 4.20, at 0, 1, 2, and 3 V bias, respectively. The PN-junction loss owing to the free carrier absorption was estimated from the measured insertion loss of the MZM and other passive silicon devices. The insertion loss of the PN-PS (denoted as white dashed box in Fig. 6(a)) was 3.31, 3.14, 3.06, and 2.98 dB, resulting in the PN-junction loss of 8.10, 7.29, 6.90, and 6.52 dB/cm at 0, 1, 2, and 3 V bias, respectively. The undoped waveguide loss of the PN-PS was 1.61 dB where the meandering structure is responsible for 1 dB.

A microwave equivalent circuit model of the differential-drive MZM is shown in Fig. 6(c), as referred from [36,37]. The MZM has four electrical ports: two input ports and two output ports. Because the upper and lower arms are perfectly symmetrical, we describe only one of the two arms as follows: the source voltage, source impedance, input impedance, and termination impedance are denoted by ${V_S}$, ${Z_S}$, ${Z_{in}}$, and ${Z_T}$, respectively. The PN-junction waveguide of each segment is modeled as a series RC circuit (denoted as ${R_{pn}}$ and ${C_{pn}}$) under the condition that the PN-PS operates in depletion mode. Series RC circuits are periodically shunted to the transmission line, where they are treated as lumped elements because of the short period of the segment compared with the microwave wavelength. RF pads and transitions for the electrical inter-connections were inserted.

To characterize the frequency response of the MZM, we measured electrical/electrical (E/E) and electrical/optical (E/O) S-parameters using an Agilent N5225A network analyzer and an N4373D lightwave component analyzer. Transmission line parameters such as the propagation constant (${\gamma _m}$), characteristic impedance (${Z_0}$), microwave attenuation (${\alpha _m}$), and index (${n_m}$) are extracted from the measured S-parameters based on a general transmission line model [36,37]. Because there is a negligible amount of cross-coupling between the two CPW electrodes owing to their large separation with a wide center ground [38], we measured only the single-ended S-parameters for one of the MZM arms. Figure 7(a) shows that the measured E/E S11 response decreased as the reverse PN bias voltage increased from 0 to 3 V. This can be explained by the reduced ${C_{pn}}$ that consequently increases ${Z_0}$ toward 50 Ω, as shown in Fig. 7(c). It is obvious from Fig. 7(d) that microwave index decreases as the bias voltage increases, and it varies from 3.86 to 3.66 between 5 to 40 GHz at 3 V bias. These values are slightly lower than the simulated group index of the optical waveguide (${n_o}$) of 3.96 [39]. Figure 7(b) shows that the E/E S21 response improves as the reverse bias increases. The achievable 6.4 dB E/E bandwidth was increased to 35.8 GHz. The E/E S21 responses were normalized to 0 dB at a frequency of 10 MHz.

 

Fig. 7. Measured and calculated S-parameters and transmission-line parameters. (a) E/E S11, (b) E/E S21 responses, (c) microwave index, and (d) characteristic impedance for various PN reverse bias voltages (0, 1, 2, and 3 V).

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The measurement results were compared with the calculated results based on the microwave equivalent circuit model. We followed the method of analyzing the frequency response of the traveling-wave modulator suggested by [37]. First, the RF characteristics of the segmented transmission line without PN-junction loading were simulated based on ADS Momentum. The S-parameter results were thereafter transformed to the transmission matrix ${T_0}$ (called the ABCD matrix). The ABCD matrix of the PN-junction waveguide ${T_a}$ was established using the estimated ${R_{pn}}$ and ${C_{pn}}$ values. The entire ABCD matrix is obtained by multiplying all the matrices ${T_1}{({T_a}{T_0})^{N - 1}}{T_a}{T_2}$, where ${T_1}$ and ${T_2}$ are the ABCD matrices of the input and output RF pads and transitions, respectively. Finally, it is converted to S-parameters. We performed several iterations to determine the correct ${R_{pn}}$ and ${C_{pn}}$ values, where the calculated curves were suitably matched with the measured ones (see dotted-lines in Figs. 7(a), 7(b), 7(c), and 7(d)). The estimated ${R_{pn}}$ value is 1.2 Ω·cm, and the ${C_{pn}}$ values are 0.37, 0.29, 0.26, and 0.23 fF/µm at the reverse bias of 0, 1, 2, and 3 V, respectively. Compared with a previous study [40], the junction capacitance of our MZM is slightly larger that results from the higher PN doping concentrations.

The E/O S21 response (that is, modulation response) is obtained from the extracted transmission line parameters such as ${\gamma _m}$, ${\alpha _m}$, ${n_m}$, and $\textrm{}{Z_0}$ from the calculated S-parameters of the PN-junction loaded transmission line. The modulation response is expressed in [41] as follows:

Figure 8 shows the measured and calculated E/O S21 responses at a reverse bias voltage of 3 V. For the measurement, each arm of the MZM is terminated with a 50 Ω resistor. The result indicates that the 3 dB E/O bandwidth is not able to reach the corresponding 6.4 dB E/E bandwidth (purple line). By curve fitting the E/O S21 response (see dashed-line), the 3 dB E/O bandwidth was estimated to be ∼20 GHz. The modulation response calculated based on Eq. (3) also shows a limited bandwidth of 21.7 GHz (blue line). It should be noted that the strong ripples were observed in the measured E/O S21 response unlike the calculated one, but the source is not yet understood and investigations are ongoing. If ${n_o}$ is reduced to 3.96 that corresponds to straight optical waveguides, the bandwidth can be increased up to 33.7 GHz (see red line), almost reaching the 6.4 dB E/E bandwidth. We have found that the limited bandwidth of our MZM is mainly attributed to velocity mismatch resulting from the additional lengths of the meandering optical waveguide. In future work, further refinements will be considered to achieve a higher bandwidth by adopting straight optical waveguides without a meandering structure. As an alternative to slot-line mode suppression, G-tie electrode structures can be introduced to the MZM design where two ground electrodes of the CPW transmission line are periodically connected [38]. In addition, the E/O bandwidth can be enhanced by a termination impedance smaller than the characteristic impedance of the MZM (${Z_T}$ < ${Z_0}$) [40,42]. This is also confirmed in our calculated results, showing an E/O bandwidth larger than 40 GHz, with a 30 Ω termination (see brown line).

 

Fig. 8. Measured and calculated E/O S21 responses of a stand-alone MZM at PN reverse bias voltage of 3 V.

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4.2 53 GBd PAM-4 eye performance

We evaluated the 53 GBd PAM-4 eye performance of the stand-alone MZM using an experimental setup, as shown in Fig. 9(a). An SHF 12104A pulse pattern generator delivered a 4 × 26.5625 Gb/s pseudorandom binary sequence (PRBS) with a pattern length of 2¹⁵–1 to the SHF 616A 4:1 PAM multiplexer, where a pair of differential PAM-4 signals at 53.125 GBd was generated. The PAM-4 signals were amplified by a pair of SHF S807C 50 GHz linear amplifiers (LAs) and subsequently fed to the MZM through a GGB 50 GHz GSGSG dual probe. In addition, a pair of bias-tees and tunable delay lines were inserted to apply a DC bias voltage of 3 V to each arm and calibrate the timing skews between the differential signal lines. Considering the driver IC to be packaged, we adjusted the amplification gain of the LAs and chose suitable attenuators to obtain a differential peak-to-peak voltage of 3.5 V_ppd. Figure 9(b) shows the measured eye diagrams of the PAM-4 electrical signal and inverse signal at P_E1 and P_E2 in Fig. 9(a), respectively, by using a Keysight N1000A digital communication analyzer (DCA). The electrical port of the DCA features an input impedance of 50 Ω. The peak-to-peak voltages of the electrical signal and inverse signal are respectively ∼1.7 and ∼1.8 V_pp, resulting in a differential swing voltage of ∼3.5 V_ppd. The rise time and fall time of the electrical signal (inverse signal) were measured to be ∼10 (∼8) and ∼8 (∼8) ps, respectively. The widths of the lower, middle, and upper eyes (denoted as Eye 0/1, Eye 1/2, Eye 2/3 in Fig. 9(b)) of the signal (inverse signal) were ∼5.5 (3.5), ∼6.1 (5.5), and ∼5.1 (5.6) ps, respectively.

 

Fig. 9. (a) Experimental setup for the eye diagram measurement of 53.125 GBd PAM-4 optical signal, (b) measured electrical eye diagrams of the driving signals, (c) measured optical eye diagrams with a scope 26.5625 GHz Rx filter, and (d) after a scope TDECQ equalizer.

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For the optical eye diagram measurement, CW light emitted from an external cavity laser (ECL) propagates to the MZM through an SMF and a polarization controller as shown in Fig. 9(a). The lasing wavelength of the ECL was set to the quadrature point of the MZM (1302.94 nm). The modulated optical signal was sent to an input optical port of the DCA. O-band grating couplers are used for the input/output optical interfaces. Figure 9(c) shows an accumulated eye diagram of the 53.125 GBd PAM-4 optical signal with a scope 26.5625 GHz Rx filter used for a dispersion eye closure quaternary (TDECQ) measurement. Because our MZM features a limited E/O bandwidth, the eye performance was severely degraded by the Rx filter. However, aided by a scope TDECQ equalizer, the clear eye openings were observed as shown in Fig. 9(d). The average outer extinction ratio (ER) and TDECQ were measured to be 5.07 dB and 1.12 dB, respectively. In this measurement, we used a custom TDECQ equalizer with a five-tap equalizer built in the DCA. The only difference from a standard TDECQ measurement compliant with IEEE 802.3cd [43] is that the input bandwidth of aliased noise processing is set to 10 MHz instead of 26.5625 GHz (that is, negligible amount of aliased noise). Considering the eye diagram result shown in Fig. 9(d) as a reference, we investigated the performance of the proposed Tx.

5. 53 GBd PAM-4 SiPh transmitter

5.1 MZM-integrated transmitter with silicon capacitors

Without integrating the LD and packaging the driver IC, we demonstrated a 53 GBd PAM-4 SiPh Tx (that is, MZM-integrated Tx) on the PCB, as shown in Figs. 10(a) and 10(b). This study aims to assess the performance of the MZM-integrated Tx and the impact of the SCs. The overall architecture of Tx follows that depicted in Figs. 1(a) and 1(b). The size of the Tx die is ∼2.87 × 7.6 mm². Because the LD was not integrated, the optical interfaces of the Tx die were modified by adding an EC for external light feeding. Furthermore, we used a four-channel fiber array unit (FAU) including two polarization-maintaining fibers for loopback optical modulation (denoted as P2 and P3 in Fig. 10(a)) and two SMFs for the optical alignment between the FAU and Tx die (denoted as P1 and P4 in Fig. 10(a)). The FAU is bonded to the Tx die after optical alignment. In this demonstration, the bonding area reached ∼40% of the entire Tx die size; nonetheless, we confirmed that it will be reduced by more than half, while guaranteeing a die-shear force above 2 kgf.

 

Fig. 10. (a) Image of the MZM-integrated Tx, (b) magnified microscope image, and measured 53.125 GBd PAM-4 eye diagrams (c) without SCs and (d) with SCs.

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The MZM-integrated Tx die and PCB were electrically connected through wire bonding, as shown in Fig. 10(b). The MZM has the same PN-PS as the stand-alone silicon modulator, as described in Section 4. The MZM has no intentional phase delay between the two arms (that is, balanced MZ interferometer), and the transmission line of each arm is terminated with a 50 Ω on-chip resistor. Three SC dies (SC0, SC1, and SC2) are wire-bonded to the termination resistor and upper and lower RF ground electrodes of the MZM, respectively. Among the various capacitors, we select Murata 3D SCs that possess superior features of not only broadband operations, but also high density (that is, capacitance per size). Compared with conventional 2D capacitors whose capacitance values depend only on the electrode surfaces, an internal tripod structure enables the 3D SCs to increase the effective surface area at a given size [44]. The SCs exhibited a capacitance of ∼10 nF with a compact size of ∼300 × 600 µm². They are placed and glued to each SC recess formed by the deep trench process. Favorably, the SCs featured a thickness of ∼100 µm, almost the same as the depth of the SC recess, considering the bonding epoxy thickness simultaneously. Thus, the contact pads of the SCs and Tx die are at the same altitude for short-wire bonds.

We experimentally measured a 53.125 GBd PAM-4 eye diagram of the MZM-integrated Tx to examine the performance improvement of the SCs. In this experiment, P2 and P3 of the Tx in Fig. 10(a) were connected to the optical ports of the ECL and DCA (denoted as P_ECL and P_DCA in Fig. 9(a)), respectively. The lasing wavelength of the ECL was set to 1310 nm, and the MZM was biased at the quadrature point by manipulating the TOPSs. The DC supply voltages ${V_{MZM}}$ and ${V_{RT}}$ were both set to 0 V, and thus, a reverse bias voltage of 3 V was applied to each arm of the MZM through the bias-tee. The other experimental setups were the same as those shown in Fig. 9(a). Figures 10(c) and 10(d) show the results of the optical eye diagram without and with SCs, respectively. Evidently, SCs significantly improve eye openings with a reduced TDECQ value by 1.16 dB. With SCs, the TDECQ value was similar to that of the stand-alone MZM. The ER was measured to be ∼4.82 dB and ∼5.02 dB without and with SCs, respectively. Even though 0.1 µF surface-mounted device (SMD) capacitors (denoted as C1 and C2 in Fig. 10(b)) are placed on the PCB near the Tx die, it is insufficient to minimize the parasitic inductances caused by the on-chip and on-board routing lines, including the wire bonds.

To understand the effect of the SCs in more detail, we measured the E/O S21 and E/E S11 frequency responses of the MZM-integrated Tx. We compare the three Tx schemes as follows: i) without the SC, ii) with SC1 and SC2, and iii) with all SCs including SC0. The RF measurement setup was the same as that described in Section 4.1. The results indicated that the E/O S21 responses were comparable for all three cases, as shown in Fig. 11(a). In the cases of i) and ii), the 3 dB E/O bandwidth was measured to be ∼21.5 GHz and in the case of iii), the bandwidth increased slightly to ∼22.6 GHz. These results were similar to those of the stand-alone MZM. Meanwhile, the difference among the three cases is evident in the E/E S11 response, as shown in Fig. 11(b). Without the SC, a high reflection of more than 10 dB was observed in the frequency range of several gigahertz (black line in Fig. 11(b)). As all SCs are used, the in-band RF reflections can be noticeably reduced below 10 dB, except for the small peak at 8 GHz (red line in Fig. 11(b)). Compared with case ii), we observe that SC0 contributes more to the reduction in the E/E S11 response (compare the red and blue lines of Fig. 11(b)). Similar observations to our experimental results have been reported in a previous study [30]. In the reference, the simulated eye performance was improved by the reduced S11 reflections with a refinement of the MZM termination, while there was extremely small change in the E/O bandwidth. Unlike the simulation results in the reference, our SC0 is not able to reduce the out-of-band RF reflections (>35 GHz). This is probably due to the residual inductance caused by the wire bonds. We expect that it will be greatly reduced via flip-chip bonding in future work.

 

Fig. 11. Measured S-parameters of the MZM-integrated Tx: (a) E/O S21 and (b) E/E S11.

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5.2 Fully-integrated transmitter for 106-Gb/s real-time operation

Finally, we implement a fully-integrated Tx with a hybrid flip-chip bonded laser operating at 106 Gb/s. As shown in Fig. 12(a), the LD (NeoPhotonics, DFB Laser Diode w/SSC) is flip-chip integrated into the Tx die. A driver IC (NeoPhotonics, KGA9106) was packaged on the PCB. The high-speed electrical lines of the PCB and Tx die were connected to the input and output pads of the driver IC through wire bonds, respectively. The driver IC features a 53 GBd baud rate, a 3 dB electrical bandwidth of ∼35 GHz, and an output amplitude of 3.5 V_ppd. These were guaranteed for a load impedance (${Z_{load}}$) of 30 Ω. Compared with the MZM-integrated Tx described in Section 5.1, the fully-integrated Tx features ∼20% longer PN-PS of the MZM, and each arm is terminated with a 33 Ω on-chip resistor. These effects compensate for each other, and thus, the changes in the bandwidth and modulation efficiency are not noticeable. Our Tx accommodates the optimum DC power supply voltage to the MZM and the driver IC. As ${V_{RT}}$ of 5.37 V is applied to the termination resistor of the MZM, the driver IC operates at the optimum ${V_{OCM}}$ of 3.8 V, where a current of ∼47.5 mA flows through the signal electrode and the on-chip resistor. ${V_{MZM}}$ is set to 0.8 V, such that the reverse bias of 3 V is applied to the PN-junction of PN-PS. The MZM is thereafter driven by a pair of differential 53 GBd PAM-4 signals from the driver IC. The modulated optical signal was launched into the SMF of a single-channel FAU. The average launch power was measured to be –1.5 dBm at an applied current to the LD of ∼80 mA, satisfying the MSA specifications [4].

 

Fig. 12. (a) Image of the fully-integrated SiPh Tx with the hybrid laser and the driver IC packaged on the PCB and measured 53 GBd PAM-4 optical eye diagram (b) with driver IC packaging, (c) with reference 50 GHz LAs for comparison.

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We evaluated 53 GBd PAM-4 eye performance of a fully-integrated Tx. In this experiment, the differential output ports of the PAM multiplexer shown in Fig. 9(a) are directly connected to each RF connector of the fully-integrated Tx (shown in Fig. 12(a)). Figure 12(b) shows the clear eye openings with the ER of ∼8.04 dB. Nevertheless, the TDECQ value exceeded the measurement limit. The reason for the high ER but poor TDECQ is the impedance mismatch between the MZM and the driver IC. As mentioned earlier, the driver IC requires a load impedance of 30 Ω to operate at a bandwidth of ∼35 GHz and a swing voltage of 3.5 V_ppd. However, the input impedance (${Z_{in}}$) of the MZM expressed by Eq. (4) varies from ∼36 to ∼50 Ω (not shown) that is larger than the required ${Z_{load}}$, where ${Z_T}$ value of 33 Ω and ${Z_0}$ in Fig. 7(c) are considered. Based on the simulation results from the driver IC manufacturer, we found that the driver IC relies on a tradeoff between the bandwidth and voltage gain according to the load impedance. The results indicate the bandwidth of 35.5, 26.4, and 16.6 GHz and voltage gain of 19.6, 20.7, and 22.4 dB at the load impedance of 35, 40, and 50 Ω, respectively. Thus, we can understand that TDECQ degradation is caused by the reduced driver bandwidth of <35 GHz owing to the higher ${Z_{in}}$ than 30 Ω. The high ER can also be explained by the applied swing voltage on the MZM greater than 3.5 V_ppd, resulting from the increased voltage gain. In future development, TDECQ performance will be improved by reducing ${Z_0}$ of the MZM to 30 Ω and choosing on-chip termination with either 30 or 25 Ω at the cost of reduced ER.

For comparison, we also measured the eye diagram using a pair of SHF 50 GHz LAs instead of packaging the driver IC. In this experiment, we employed another PCB with the transmission lines extended by the length of the driver IC die to maintain the same length of wire bonds to the Tx die. As shown in Fig. 12(c), the ER and the TDECQ are measured to be 4.86 and 1.55 dB, respectively, when the MZM operates with the electrical setup denoted by the dashed box in Fig. 9(a). The differential output swing voltage of the LAs was adjusted to be 3.5 V_ppd with a 50 Ω load. Because ${Z_{in}}$ of the MZM is lower than 50 Ω, the applied swing voltage on the MZM was estimated to be smaller than 3.5 V_ppd. As referred from [40], the reduction ratio of the swing voltage is expressed as $2{Z_{in}}/({{Z_{in}} + 50\Omega } )$. Compared with previous result in Fig. 10(d), the TDECQ is increased by 0.51 dB. That is mainly attributed to the two RF interconnections i) between the Tx die and the PCB (that is, wire bonds) and ii) between the PCB and RF connectors.

To verify the feasibility of the fully-integrated Tx, we demonstrated a 106 Gb/s real-time operation, as shown in Fig. 13(a). In this study, we used a commercially available 4 × 53.125 GBd PAM-4 DSP chip (Inphi, IN010C50-MD02 Porrima 53 GBd 8:4 PAM-4 DSP). The DSP chip accommodates 8 × 26.5625 GBd PAM-4 signals at the host-side interface and converts them to 4 × 53.125 GBd PAM-4 signals at the line-side interface (denoted as LTX0:3). The DSP chip provides the ability to generate PRBS patterns with a length of 2³¹–1 to check BER. In addition, it enables the provision of Gray coding and pre- and post-equalization functions that correct the distortion of the signals. In this demonstration, one of the four line-side signals from the DSP chip (that is, LTX0) excites the fully-integrated Tx referred to as a device under test, and the others (that is, LTX1:3) are directly sent back to the DSP chip itself. The 53.125 GBd PAM-4 optical signal is transmitted and subsequently received by a reference optical receiver (Rx) through the SMF. The Rx consists of a 45 GHz InGaAs/InP-based PIN-PD and a 48 GHz transimpedance amplifier (TIA) that has an output swing voltage of ∼650 mV_ppd. After receiving the 53.125 GBd PAM-4 electrical signals (that is, LRX0), the DSP chip counts the total number of transmitted/received bits and error bits. This BER measurement was repeated until the optimal BER was obtained. The parameters of the DSP chip that affect the BER performance on the entire data path are as follows: i) pre-equalization, ii) PAM-4 eye inner/outer ratio, iii) PAM-4 eye height, iv) variable gain adaptation tracking, and v) post-equalization. At the optimal BER, three-tap feed forward equalizer (FFE) coefficients (–90, 600, –50) were obtained for pre-equalization. The measured optimal BER curve is shown in Fig. 13(b). An Rx sensitivity of –5 dBm was achieved at a KP4 forward error correction (FEC) threshold of 2.4 × 10^–4. Furthermore, the measured BER reaches ∼1 × 10^–6 that is sufficiently lower than the FEC threshold when the Tx outputs a maximum optical power of –1.5 dBm. Under the DSP settings for the optimized BER, we measured the optical eye diagram as shown in inset of Fig. 13(b). Because of a poor quality of the DSP output signals, the TDECQ value still exceeded the measurement limit. Nevertheless, we achieved the BER as low as ∼1 × 10^–6 with the help of the three-tap FFE.

 

Fig. 13. (a) Experimental setup for demonstrating a 106 Gb/s real-time operation and (b) measured BER curve.

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6. Conclusion

We proposed and successfully demonstrated a fully-integrated SiPh Tx with a flip-chip bonded hybrid laser for 106 Gb/s per lane applications. The Tx die was fabricated using a highly accessible commercial SiPh foundry. The LD in the recess of the Tx die was butt-coupled to the silicon waveguide, where the optical power was greater than 10 dBm to at an applied current of 84 mA. Considering the adaptive solder design in the LD recess, the calculated probability of success of flip-chip bonding above 0.97 was accomplished by compensating for fabrication variations. In addition, we experimentally verified that the large misalignment tolerances at 1 dB power penalty in the horizontal and vertical directions were 2.3 µm and 1.2 µm, respectively, that is considerably larger than the accuracy of the recent advanced bonders.

Integrated with the MZM, the SiPh Tx could accommodate 53 GBd PAM-4 signal (that is, 106 Gb/s). We experimentally evaluated the RF characteristics and eye performance before integrating the LD and packaging of the driver IC. The experimental results clearly exhibited open PAM-4 optical eyes with an ER above 5 dB at a drive voltage of 3.5 V_ppd that corresponds to the minimum output swing voltage of the driver IC. To decouple the parasitic inductance of the Tx, our MZM-integrated Tx was integrated with high-density off-chip SCs. The in-band S11 frequency response was significantly suppressed below –10 dB, leading to a TDECQ improvement of 1.16 dB. Finally, we confirmed the feasibility of the fully-integrated Tx with the hybrid flip-chip bonded laser to realize 100 G/lane SiPh transceivers. For this purpose, the driver IC die was also packaged on the PCB. In conjunction with the commercially available DSP chip, a 106 Gb/s real-time operation was successfully demonstrated by achieving a BER below the KP4-FEC threshold (2.4 × 10^–4) at a receiver sensitivity of –5 dBm. At the maximum Tx optical output power of –1.5 dBm, the measured BER almost reached 1 × 10^–6.

In future work, we will attempt to achieve a perfect velocity match of the MZM for a higher electro–optic bandwidth. Instead of using the meandered optical waveguide, G-tie structures [38] will be introduced to suppress undesired RF modes. We will further optimize the input impedance of the MZM-integrated Tx considering the required load impedance of the driver IC. Furthermore, to minimize the parasitic inductance, the SCs will be flip-chip bonded to the Tx die with solder bumps.