Abstract
We have developed a 5 × 5 mm2 compact silicon-photonic receiver with a 28-nm CMOS transimpedance-amplifier (TIA) chip. The receiver chip was designed using a photonics—electronics convergence design technique for the realization of high-speed and high-efficiency operation because the interfaces of the optical and electrical components greatly influence the receiver characteristics. Optical pins were used to obtain easy optical alignment between the multimode fibers and the germanium photodetectors. An aluminum stripline between the PD and the TIA enhanced the 3-dB bandwidth because its characteristic impedance is greater than the TIA input impedance. Coplanar waveguides (CPWs) on the etched SOI wafer achieved a low insertion loss because the overlap between the electric fields of the CPWs and the silicon layer was reduced. We demonstrated 25-Gb/s error-free operation at both 25 and at 85 °C. The minimum sensitivities and power consumptions of the receivers were −11.0 dBm and 2.3 mW/Gb/s at 25 °C and −10.2 dBm and 2.5 mW/Gb/s at 85 °C, respectively. These results show that our receiver can be applied for practical use at high temperatures.
© 2015 OAPA
PDF Article
More Like This
Silicon photonic receiver and transmitter operating up to 36 Gb/s for λ~1550 nm
Jiho Joo, Ki-Seok Jang, Sang Hoon Kim, In Gyoo Kim, Jin Hyuk Oh, Sun Ae Kim, Gyu-Seob Jeong, Yoonsoo Kim, Jun-Eun Park, Sungwoo Kim, Hankyu Chi, Deog-Kyoon Jeong, and Gyungock Kim
Opt. Express 23(9) 12232-12243 (2015)
Experimental demonstration of a 160 Gbit/s 3D-integrated silicon photonics receiver with 1.2-pJ/bit power consumption
Dingyi Wu, Dong Wang, Daigao Chen, Jie Yan, Ziyue Dang, Jianchao Feng, Shiping Chen, Peng Feng, Hongguang Zhang, Yanfeng Fu, Lei Wang, Xiao Hu, Xi Xiao, and Shaohua Yu
Opt. Express 31(3) 4129-4139 (2023)
Cited By
Optica participates in Crossref's Cited-By Linking service. Citing articles from Optica Publishing Group journals and other participating publishers are listed here.