Abstract
Accelerated bit-error-ratio (BER) measurement techniques using specialized test equipment are widely used for rapidly verifying the low BER (< 10^-12) of high-performance optical links. However, once these links are deployed in the field, it takes days to weeks to complete such BER measurements using a conventional testing method. This paper describes an optical transceiver architecture with on-chip accelerated BER measurement mechanics that reduces" in the field"BER testing time to minutes. The approach described in this paper uses an integrated interference generator to degrade receiver performance and raise the BER to a range that allows a substantially reduced measurement time. Values of BER versus the amount of interference are then extrapolated to the point of zero artificial degradation for actual BER. A 0.5-µm complementary metal-oxide-semiconductor, 2-Gb/s, four-channel optical transceiver chip was designed, fabricated, and tested to serve as a vehicle for verifying the concept. The experimental results show excellent agreement between the extrapolated and actual BER values. The architecture described here points to a practical built-in self-test capability for optical links within high-performance digital systems, specifically in board-and backplane-level interconnections.
© 2004 IEEE
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