Abstract

The carry-free property of modified signed-digit addition is discussed, and a space-position–logic-encoding scheme is proposed, which not only makes best use of the convenience of binary (0, 1) logic operation but is also suitable for the trinary (1,0,1¯) property of modified signed-digit digits. Based on the space-position–logic-encoding scheme, a fully parallel modified signed-digit adder and subtracter is built by use of optoelectronic switch modules and butterfly interconnections; thus an effective combination of a parallel algorithm and a parallel architecture is implemented. The effectiveness of this architecture is verified by both simulation and experimental results.

© 1994 Optical Society of America

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