1. Introduction

Semiconductor-heterostructure-based science and technology have made remarkable development in various fields from basic research to practical applications [1–3]. Because of the one-dimension structure with a nanoscale diameter [4], semiconductor nanowires have shown high potential applications in many research fields including electronics [5], photonics [6], photoelectrochemistry [7], etc [8–10]. In contrast to the film-based structure, a nanowire-based structure grown by bottom-up approach has exhibited high capability to form a dislocation-free interface for lattice-mismatch heterostructures [11–15]. Such high ability to accommodate strain by lattice distortion opens up new opportunities including new material combinations for heterostructures [16–18] and ultra-high-strain-layer contained nanostructures [19–21]. As an extremely important wavelength range, i.e., telecom band (1.2 µm ∼ 1.6 µm) in our optical-fiber-based modern society [22–24], nanowire-based light emitting diodes (LEDs) working in telecom band have been realized by a combination of In(Ga)P and In(Ga)As materials [25–27].

Because of its high controllability of site, interface abruptness, and quantum heterostructure, a vapor-liquid-solid (VLS) [28,29] bottom-up approach has been widely used for nanowire growth of various materials and related heterostructures [12,30–32]. The VLS approach has been used for development of various optoelectronic devices working in visible and near infrared wavelength range [10,33–38]. However, very few reports about VLS-nanowire-based optical devices have been published in telecom band range [27]. This remains challenging mainly due to difficulties in limited material choices, growth and structural control. Despite a lattice mismatch as high as ∼3%, InP/InAs heterostructure has been realized in nanowire structure [15,16] even with multiple (∼ 400) heterostructures by indium-particle-catalyzed VLS mode [39]. The band gap engineering for InAs segment by quantum confinement effect enables to extend the working wavelength into telecom band range [27,39]. However, due to the inadequate understanding of nanowire structure, nanowire-based optical devices working in telecom band range exhibit a degraded electrical property [27]. Towards practical device applications, it is crucial to enhance understanding of nanowire structure and to improve the optoelectronic performance of InP/InAs nanowire-based devices working in telecom band range.

In this work, we report enhanced optoelectronic property of p-i-n structured InP/InAs heterostructure nanowire LED devices. As-grown InP/InAs nanowire-based devices show electroluminescence in telecom-band range at room temperature. Nevertheless, these devices exhibit relatively high leakage current and a low open-circuit voltage (V_OC) of 0.084 V. We firstly clarify that the high leakage current is caused by the simultaneous deposition of conductive shell layer on nanowire sidewalls during the axial VLS-mode growth. We then show that the device exhibits an increased V_OC of 0.412 V and largely reduced leakage current after removing the conductive shell layer through a piranha chemical etching. By doing analysis about ideality factor, we further confirm the device performance enhancement and gain an insight into the device circuits for future development.

2. Nanowire material growth and device fabrication method

We grew InP/InAs heterostructure nanowires via self-catalyzed VLS mode using indium catalyst particles in a metalorganic chemical vapor deposition (MOCVD) system [27]. Indium particles were formed on a p-type InP (111)B substrate (size: 1 cm × 1 cm) by introducing trimethylindium (TMIn) source material at 360 °C substrate surface temperature. These particles act as seeds for subsequent nanowire growth process. TMIn and tertiarybutylphosphine (TBP) were then simultaneously introduced at 350 °C to initiate InP nanowire growth in indium particle catalyzed VLS mode. After initial 30-min growth of Zn-doped InP segment (height: 3.7 µm), we grew InAs multiple quantum disk (InP/InAs: 10 periods) segment followed by 30-min growth of S-doped InP segment (height: 4.0 µm). The thickness of an InAs layer and an InP barrier layer are 9.0 ± 1 nm and 25.6 ± 1 nm, respectively. InAs thickness of an InAs quantum disk as thin as ∼ 9 nm, which is quite smaller than the Bohr radius (∼34 nm) of bulk InAs, causes quantum confinement along the axial direction and thus enables luminescence in telecom band.

The flow rates of TMIn and TBP were 3.03 and 803 µmol·min⁻¹, respectively. For InAs quantum disk growth, the flow rates of TMIn and TBAs were 0.98:290 µmol·min⁻¹. Diethylzinc (DEZn) was used as p-type conduction dopant source with a flow rate 0.48 µmol·min⁻¹. Di-tert-butyl Sulfide (DTBS) was used an n-type conduction dopant source with a flow rate of 0.33 µmol·min⁻¹. We used H₂ purified by palladium alloy membrane purifier as a carrier gas for all source materials.

We analyzed morphology of InP/InAs nanowires by scanning electron microscopy (SEM, Car Zeiss, Ultra-55) (Figs. 1(a) and 1(b)). Nanowires are vertically aligned on InP (111)B substrate. Each nanowire shows uniform diameter and has an indium particle at its tip, indicating a dominant VLS-catalyzed growth. For electrical device fabrication, we embedded vertically aligned nanowires into transparent insulating material (benzocyclobutene, BCB) by spin-coating and hardening process (Fig. 1(c)). We then used reactive ion etching for BCB material removal to expose the nanowire top surface for subsequent electrical contact. Transparent indium tin oxide (ITO) was then deposited on the upper side for electrical contact with n-type InP segments (Figs. 1(d)-(e)). AuZn/Au (thickness: 24/44 nm) was deposited on the back side for electrical contact with p-type InP substrates. We measured electrical characteristics of nanowire devices by a semiconductor parameter analyzer (Keithley, 4200A-SCS) at room temperature.

 

Fig. 1. (a and b) SEM images (tilt: 38°) of InP/InAs nanowires with a p-i-n structure containing 10 InAs quantum disks vertically aligned on a p-type InP (111)B substrate (density: 3.0 × 10⁵mm⁻²). The inset in (b) schematically shows the p-i-n structure. The purple-color area is S-doped InP segment. The blue-color area is Zn-doped InP segment. The light-yellow-color area is potentially existing shell segment. (c) Schematic diagram of a device structure for electrical measurement. (d and e) SEM images (tilt: 45°) of a LED device with embedded InP/InAs nanowires in transparent insulating BCB material. One can see nanowires covered with ITO material for n-type InP segment contact. (f) Electroluminescence spectra of a single nanowire under a bias of 3 V. The inset shows the nanowire luminesce image in current injection taken by a InGaAs camera in a micro-PL setup [40]. (g) Electrical characteristics of a device. The I-V curve shows a p-i-n diode feature. While there is a relatively large leakage current (∼ 20 mA) under a reverse bias of 1.5 V.

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It is crucial to find appropriate parameters to evaluate optoelectronic properties of nanowire p-i-n junction devices. electroluminescence enhancement may be used as one of key parameters. However, electroluminescence intensity is affected by many factors, including nanowire shape, indium catalyst particle presence, leakage current, nanowire variation, etc. On one hand, when a photodetector is set on upper side of a nanowire device, electroluminescence intensity represents how much light is collected from the upper side. However, when there is an indium particle at a nanowire tip, most electroluminescence doesn’t emit from the upper side and is reflected into the substrate along the nanowire waveguide. Even the indium particle is removed, part of electroluminescence is still reflected due to the refractive index difference between air and InP nanowire [27]. On the other hand, electroluminescence intensity is also affected by nanowire variation. electroluminescence intensity is basically inhomogeneous though nanowires had a same device fabrication process [27]. Issues affecting nanowire variation include diameter, active region crystalline quality, contact resistance, etc. We realize electroluminescence enhancement is not a suitable parameter to evaluate optoelectronic properties. That is why we focus on the evaluation of optoelectronic properties by using open-circuit voltage and leakage current parameters. The two parameters are basically determined only by the p-i-n junction quality. The two key parameters fundamentally decide the basic property of p-i-n junction and has straightforward effect on nanowire-based solar cells, photodetectors, lasers, and LEDs. Furthermore, analysis of leakage current under reverse bias condition provides more in-depth insight onto devices, which is not accessible by device operation under forward bias condition.

3. Results and discussion

Under a forward bias, a nanowire LED device shows electroluminescence in O-band of telecom band range (Fig. 1(f)). This indicates that the recombination of injected electrons and holes occurs in the InP/InAs multiple quantum disk region. The quantum confinement effect in InAs quantum disks (thickness: 6.8 - 9 nm) along the axial direction enables the luminescence spectrum in telecom band (1.2 µm – 1.6 µm). When reversely biased, the device exhibits a current as high as 20 mA at −1.5 V bias, indicating presence of a large leakage current. Such high leakage current makes it hardly possible to make high-performance optical devices towards practical optoelectronic applications. It is required to clarify the origin of such a high leakage current and to improve optoelectronic performance for these nanowire-based devices.

To gain the understanding about the origin of such large leakage current, we considered possible nanowire structures (Fig. 2(a)). In addition to the dominant VLS-catalyzed growth along axial direction, the growth on sidewalls along radial direction via non-VLS mode unavoidably occurs. The growth along the radial direction usually results in a high-quality monocrystalline shell layer on nanowire sidewalls. Nevertheless, the current growth temperature at 350 °C is too low for growth of high-quality monocrystalline shell layers of both InP and InAs materials (normally > 600 °C is needed). Another option is that the shell layer is not high-quality monocrystalline layer grown by epitaxial mode on sidewalls, but low-quality crystalline (or non-crystalline) InP layer by deposition from raw metalorganic materials. If the shell layer is low-quality crystalline (or non-crystalline), the shell layer might be very conductive and then induces a large leakage current flow from the shell layer.

 

Fig. 2. (a) Schematic diagram of three nanowire structures, namely, ideal structure and two core-shell structures with different shells: i.e., high-quality monocrystalline shell and low-quality crystalline (or non-crystalline) shell. (b) SEM image of nanowires dispersed on a Si substrate. (c-e) Enlarged SEM images of different regions indicated in (b). Rough side layers selectively exist on side {112} faces. For the current growth condition with a growth temperature as low as 350 °C, it is almost impossible to grow high-quality crystalline epitaxial shell layer by conventional vapor phase epitaxy mode on nanowire sidewalls. The result indicates a core-shell structure with low-quality crystalline (or non-crystalline) shell.

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To clarify whether there is a shell layer grown on nanowire sidewalls, we carried out further morphology analysis. We dispersed nanowires from the as-grown samples onto Si substrates and performed morphology analysis by SEM (Figs. 2(b)-(e)). As indicated by white arrows, one can see that there are rough layers on the side {112} faces throughout the nanowire, especially at the bottom part in Fig. 2(e), indicating presence of a shell layer. Nevertheless, the side {110} faces are quite smooth, indicating no shell layer formation on these faces. There are usually stacking faults in these <111>-oriented nanowires. Due to the polarity feature, the sidewall usually consists of alternatively changed tiny {111}A and {111}B facets [41], which predominantly appear on side polar {112} faces instead of nonpolar {110} faces. In other words, side {112} faces contain nanoscale zigzag morphology of {111}A and {111}B nanofacets, while nonpolar side {110} face does not. Because of the nanoscale roughness, indium and P atoms on nanowire sides were preferentially deposited on {112} faces. We also further confirmed the presence of the shell layer by analyzing sidewall region using TEM measurement. The shell layer on {112} side faces is low-quality crystalline (or non-crystalline) and thus should be very conductive. Presumably, the conductive shell layer could be responsible for the high leakage current.

To confirm whether the shell layer is the origin of the high leakage current, we fabricated nanowire electrical devices after the shell layer removal and then compared photovoltaic properties of nanowire devices with or without the shell layer. To remove the side shell layer, we used piranha etchant. The piranha etching was carried out by the piranha solution (H₂O:H₂O₂:H₂SO₄, volume ratio of 1:1:3). Nanowire samples were immersed into the solution for 1-2 s at temperature lower than 30 °C, then were rinsed by pure water, finally were dried by N₂ gun. Figure 3 shows SEM images of nanowires before and after piranha etching. Indium particles at nanowire tips were totally removed by piranha etching. In contrast to the rough layer on {112} side faces before etching (Fig. 3(c)), nanowires show a quite smooth side surface after etching (Fig. 3 g). This indicates that the side rough shell layer has been removed by the etching process. Moreover, chemical polishing effect of piranha etchant made very smooth side faces by exposing the inside crystalline InP segment. In addition, in the InP/InAs multiple quantum disk region, there are ten grooves, directly revealing the InP/InAs structure (Fig. 3 h). These grooves are induced by faster etching rate of InAs than InP segments. The revealing of the internal multiple quantum heterostructures further indicate an effective removal of these side shell layers by the surface etching process. In addition, the result shown above actually indicates a new way to identify the superlattice-like heterostructure active layer region without using high-cost TEM measurement, which is usually necessary to analyze inside heterostructures in nanowires.

 

Fig. 3. SEM images of InP/InAs nanowires before (a-c) and after (e-h) piranha etching. Indium particles and shell layers on side surface were removed by piranha etching. The nanowire exhibits a rough layer on {112} sidewalls (c, indicated by white arrows), while the side surface becomes very smooth after etching (g and h). Due to faster etching rate of InAs segment than InP segment, surface etching process reveals the multiple quantum heterostructure region (g and h). (d) schematic diagram of nanowire structure before and after etching.

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In the etching process. nanowires were exposed into air after piranha wet etching, so nanowire surface was soon oxidized and thus create surface states, which are normally nonradiative recombination centers. This may be a serious problem for nanowires with sub-100-nm diameter for room-temperature device operation. However, noting that our nanowire diameter is basically above 1000 nm, though the InAs material in the surface region is “dead”, the InAs material in the center part is still “active”. In addition, in device fabrication process, we embedded nanowires into BCB material for encapsulation as fast as possible (usually within one hour) after piranha etching to avoid long time air exposure.

We then compare photovoltaic characteristic of nanowire devices without and with piranha etching (Fig. 4). Under a reverse bias of −1 V, the dark current is reduced from 4.58 mA to 0.078 mA by 58 times (Figs. 4(a) and 4(c)). Under visible light illumination (near one-sun intensity), V_OC is improved from 0.084 V to 0.412 V by 4 times (Figs. 4(b) and 4(d)). The largely improved V_OC is attributed to suppressed leakage current. The result is the direct evidence that the leakage current is caused by the shell layer. Once this conductive shell layer is removed by piranha etching process, the device exhibits a V_OC of 0.412 V. The improvement becomes quite clear by using logarithmic scale in current (Fig. 4(f)). Furthermore, the short-circuit current (I_SC) is improved by over 10 times with piranha etching process. These results are summarized in a table shown in Fig. 4 g.

 

Fig. 4. I-V characteristic of nanowire devices without (a and b) and with (c and d) piranha etching. The insets in (a) and (c) schematically shows corresponding device structures. (a) and (c) were taken under dark condition. Noting that the reverse current is reduced after piranha etching. (b) and (d) were taken under dark and visible light (∼one sun intensity) illumination conditions. (e) Schematic diagram of the device performance improvement by removing the side conductive shell layer (R_SH). (f) I-V of the data in (d) with the longitudinal axis in logarithmic scale. (g) Summary of leak current, V_OC, and I_SC before and after piranha etching. The V_OC is improved by 5 times after piranha etching. The I_sc increases by over 10 times after piranha etching. The photovoltaic device with piranha etching shows a filling factor of 34% with maximum power at a bias of 0.24 V and a reverse current of 395.6 µA.

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About microscopic mechanism of the shell layer, we propose the following formation model. The current growth temperature at 350 °C is too low for growth of high-quality monocrystalline shell layers of both InP and InAs materials (normally > 600 °C is needed). Another option is that the shell layer is low-quality crystalline (or non-crystalline) InP layer by deposition from metalorganic materials on sidewalls. Figure 3(c) indicates that the shell layer has a very rough surface. The result suggests that the shell is not an epitaxial growth layer, but a deposition layer. Indium and P atoms are formed from decomposition of TMIn and TBP molecules absorbed on nanowire sidewall. Because the substrate temperature as low as 350 °C make it difficult for these atoms to desorb from the sidewall, these indium and P atoms remain on the sidewall and then accumulate into a mixture of indium and P as a noncrystalline shell layer. The metallic nature of indium composition in the shell layer naturally causes high conduction. The high conduction is directly verified by the reality of high leakage current experimental result.

The improved V_OC value is still lower than that of InP nanowire photovoltaic device with a similar axial p-i-n junction (0.779 V) [42]. This is because the absorption region of our device is InP/InAs multiple quantum disk structure with telecom band luminescence instead of pure InP material. Photovoltaic devices with core-shell structure InP nanowires shows a V_OC of 0.43 V [43], which is quite low compared with those with axial p-i-n structure InP nanowires [42]. GaAs nanowire photovoltaic devices with a core-shell structure also show a low V_OC of 0.39 V [44]. These results indicate that the axial heterostructure is particularly advantageous for the suppression of leakage current because of its relatively small junction area compared with the radial heterostructure in core-shell p-i-n structured nanowires. We note that up to now, there is still no report about an axial p-i-n junction containing an InP/InAs superlattice-like active region to our knowledge. In addition, we believe that the introduction of superlattice-like heterostructure into nanowires could offer advantages over homogeneous nanowire structures for designed wavelength output.

The I-V characteristic of a photovoltaic cell under illumination, firstly developed by Shockley [1] and thus referred to as the Shockley equation, usually can be written as $I = {I_S}({e^{\frac{{eV}}{{kT}}}} - 1) - {I_L}$, where I_S is the reverse saturation current, I_L is light generated curre.t, e and k is elementary charge and Boltzmann constant, respectively. I_L is usually equal to I_S (in the case of high series resistance, I_L is less than I_S.). To describe experimentally measured characteristics of real devices, the following equation is usually used: $I = {I_s}({e^{\frac{{eV}}{{{n_{ideal}}kT}}}} - 1) - {I_L}$, where n_ideal is the ideality factor of the diode. V_OC can be obtained when I is equal to zero, i.e. ${V_{OC}} = {\raise0.7ex\hbox{${{n_{ideal}}kT}$} \!\mathord{\left/ {\vphantom {{{n_{ideal}}kT} e}} \right.}\!\lower0.7ex\hbox{$e$}} \cdot \textrm{ln}({{\raise0.7ex\hbox{${{I_L}}$} \!\mathord{\left/ {\vphantom {{{I_L}} {{I_S}}}} \right.}\!\lower0.7ex\hbox{${{I_S}}$}} + 1} )$. V_OC is reversely proportional to I_S. The suppressed reverse saturation current (Figs. 4(b) and 4(d)) directly contribute to the improvement of V_OC.

Under typical forward-bias conditions without illumination, the diode voltage (V) is V >> ${\raise0.7ex\hbox{${\kappa T}$} \!\mathord{\left/ {\vphantom {{\kappa T} e}} \right.}\!\lower0.7ex\hbox{$e$}}$, and thus the Shockley equation can be rewritten, for forward-bias conditions, as $I = {I_s}{e^{\frac{{eV}}{{{n_{ideal}}kT}}}}$. For real diodes, the ideality factor assumes values of typically, ${n_{ideal}} > 1.1$. Detailed assessment of the diode I-V characteristic and ideality factor analysis allows for the diagnosis of potential problems such as parallel and series resistance. We extracted the ideality factor from the I-V characteristic data (Figs. 4(a) and 4(c)) using the following equation: ${n_{ideal}} = \frac{e}{{kT}} \cdot \frac{1}{{{\raise0.7ex\hbox{${d({\ln I} )}$} \!\mathord{\left/ {\vphantom {{d({\ln I} )} {dV}}} \right.}\!\lower0.7ex\hbox{${dV}$}}}}$, where ${\raise0.7ex\hbox{${d({\ln I} )}$} \!\mathord{\left/ {\vphantom {{d({\ln I} )} {dV}}} \right.}\!\lower0.7ex\hbox{${dV}$}}$ has a bias dependence. Figure 5 shows the dependence of the ideality factor on the forward bias. Under low bias region (here, < ∼ 0.6 V), parallel resistance (R_P) dominates device performance. Under high bias region (here, > ∼ 1.0 V), series resistance (R_S) dominates device performance (Fig. 5(a)). For an ideal diode, the R_P should be infinitely large, and R_S should be zero. If R_P is small, leakage current is induced and n_ideal increases. This corresponds to the case of the nanowire device without piranha etching (Fig. 5(b)). For the device with piranha etching, leakage current is effectively suppressed (Fig. 4) and R_P becomes large. This leads to the reduced n_ideal (Fig. 5(b)). Under high bias region (> ∼ 1.0 V), n_ideal exhibits almost same profile (Figs. 5(b) and 5(c)), indicating R_S is almost same for the two devices. R_S is mainly determined by the electrode contact and substrate resistance, which is not affected by the surface etching process. The relatively high n_ideal under high forward bias region implies there is much space to improve the diode characteristic by optimizing fabrication process for reduction of the series resistance (R_S). The relatively low filling factor of 34% (Figs. 4(d) and 4(f)) can also be improved by optimization of the fabrication process.

 

Fig. 5. (a) Schematic diagram of the device circuit. R_p and R_s represents parallel and series resistance, respectively. (b) and (c) Ideality factor analysis of nanowire devices without (b) and with (c) surface etching under dark condition. The insets in (b) and (c) schematically shows corresponding device structures. At low bias region, the ideality factor difference is quite notable, as indicated by grey colored zone. The device performance is enhanced by removing the conductive shell layer through piranha etching process. At high bias region, the ideality factor shows an almost same profile, indicating a relatively high R_s for both devices.

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4. Conclusion

In conclusion, we realize enhanced optoelectronic property of p-i-n structured InP/InAs heterostructure nanowires with telecom band luminescence. The nanowire device with usual fabrication process exhibits a degraded electrical property (V_OC: 0.084 V) due to the relatively high leakage current (4.58 mA at −1 V bias). We clarify that the origin of the high leakage current is a highly conductive shell layer. After the removal of the shell layer through a piranha chemical etching, the device exhibits an increased electrical property (V_OC: 0.412 V) and largely reduced leakage current (0.078 mA at −1 V bias). The analysis about ideality factor further confirms the enhanced electrical performance and gains an insight into the device circuit. This work paves the way for nanowire-based high-performance optoelectronic devices working in telecom band range. Because of the feature of a very small footprint of nanowire structure, these nanowire devices have high potential to be integrated onto other platforms such us silicon complementary metal-oxide-semiconductor process and function as active photonic segments [45–47].