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Abstract
We demonstrate a power-efficient and fast thermo-optic phase shifter on a Ge platform for mid-infrared applications. Several approaches are implemented to improve the performance. Air trenches and Si-Ge multilayers with ultra-low thermal conductivity are introduced to provide thermal insulation. Few-layer graphene is used to enhance the thermal conductivity between the heater and the waveguide for efficient heat injection and subtraction. The optimized design has a power consumption of 3.9 mW and a time constant of 1.8 µs, resulting in a very small figure-of-merit of merely 7.0 mW·µs, 4 times smaller than the previously reported value.
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1. Introduction
Mid-infrared (MIR) photonics attracts much intention for chemical and biological sensing due to specific absorption features of many molecules in the MIR range [1,2]. Generally, beyond silicon on insulator (SOI) platform, MIR systems are often based on various material platforms, including Ge-on-Si, Ge-on-insulator (GeOI), Si-on-SiN, Si-on-sapphire, AlN-on-sapphire, lithium niobate-on-sapphire, SiC and suspended Si structures [3–12]. Among them, Ge is particularly promising for MIR photonics due to its transparency in a wide wavelength range up to 14.6 µm. The large refractive index of n≈4.3 of Ge allows for building compact devices [1]. The thermo-optic coefficient of Ge is about two times larger than Si, making thermal tuning more power-efficient for Ge devices.
Many on-chip functionalities require active control of the optical phase, and thermo-optic phase-shifters (TOPSs) are attractive due to their low-loss feature and relatively straightforward fabrication. Applications of TOPSs can be found in sensing, switching, optical phased arrays, quantum photonic circuits and neural networks [13–18]. One drawback of TOPSs is their slow operation, especially when the operation power is low, and the time constant is typically in a range of µs-ms [19–29], limited inherently by the slow phonon propagation in solids. Up to now, most TOPSs are demonstrated on the SOI platform. Since Si is a good conductor of heat, thermal-optical tuning is accompanied by the unavoidable heat diffusion to the substrate, resulting in energy-consuming and slow TOPSs. This issue becomes severer in MIR devices, as waveguide sizes and the spacing between the waveguide and heater need to be increased with the operating wavelength to maintain the single-mode operation and a relatively low propagation loss, which further limits the tuning speed and energy efficiency of MIR TOPSs.
Many efforts have been devoted to improve the performance of TOPSs. One common approach is to suspend the structures with air trenches and undercuts, effectively reducing the tuning power by eliminating thermal conduction pathways [19–21]. In another scheme, selected regions of Si ridge waveguides were doped to reduce the effective distance between the waveguide and heater [22]. Folded structures are also commonly used in the TOPS design, which improves the efficiency of the TOPS by maximizing overlap between the optical mode and the thermal profile. A Michelson interferometer configuration was proposed as an alternative to the Mach-Zehnder configuration in [23], which can be regarded as a special case of folded structures with the reduced TOPS length by a factor of two. Other folded structures were also demonstrated to improve power efficiency [24–26].
Recently reported TOPSs are compared in Table 1 in terms of the power required for a phase shift of π, Pπ, and the thermal time constant, τ. Pπ and τ quantify the efficiency and speed of the TOPS design. A figure of merit (FOM) is defined as the product of Pπ and τ, where the power consumption and the thermal time constant are given by [25]:
where ΔTπ represents the required temperature change for π shift, G is the thermal conductivity between the waveguide and heat sink, H is the equivalent heat capacity of the heated arm. Equations (1) and (2) work for all TOPSs. Although a fast and power-efficient design is highly desirable, it is challenging to simultaneously achieve both due to the apparent trade-off given by Eqs. (1) and (2). The product of Pπ and τ is often used to characterize the performance of a TOPS [25]: A smaller FOM with simultaneously reduced Pπ and τ is highly desirable for a high-performance TOPS. In Table 1, most designs use Si as the waveguide material, while Ge is used in Refs. [19] and [27]. A rib waveguide with geometry of A × B (C) means a width of A in µm, an etch depth of B in µm and total a thickness of C in µm.
Table 1. Recently reported thermo-optic phase shifters
The use of new materials with extremely high/low thermal conductivity provides a new way for constructing better TOPSs. One example is graphene with exceptionally high thermal conductivity. The measured thermal conductivity of suspended single-layer graphene is in the range of 600 ∼ 5000 W/m·K [36,37]. Experimental results showed that few-layer graphene (FLG) with a thickness of 5 nm has in-plane thermal conductivity of ∼600 W/m·K when encased in SiO2 [37,38]. In contrast, Si-Ge multilayers (MLs) deposited by sputtering have been demonstrated to exhibit ultra-low thermal conductivity. Owing to the phonon scattering and the interfacial thermal resistance characteristics, the thermal conductivity of the fabricated Si-Ge MLs is as low as 0.29 W/m·K when the single-layer thickness is 0.8 nm [39].
In this paper, we propose a TOPS design on GeOI platform. Our device incorporates 5-nm FLG and 200-nm Si-Ge MLs underneath the waveguide, and air-trenches with depth of 2 µm on each side of the waveguide. Such a design simultaneously allows fast and efficient heat transfer from the heater to the waveguide and prohibits heat dissipation into the surrounding environment, resulting in greatly reduced τ of 1.8 µs and Pπ of 3.9 mW. An excellent FOM of 7.0 mW·µs is obtained for the optimized design parameter, which is more than 4 times better than the reported experimental value [25].
2. TOPS geometry
The proposed TOPS design is illustrated in Fig. 1(a). The design is based on GeOI platform and operates at a wavelength of 2 µm. The TOPS length is fixed to be 100 µm. Figure 1(b) shows the cross-section of the TOPS. The Ge waveguide is designed to be single mode with 700 nm in width and 450 nm in height. Here we adopt Pt as the material for the heaters. Thanks to its large electrical resistivity [21,27], Pt heater can achieve higher heater power given the same voltage. The Pt heater is 1 µm wide and 100 µm long. In our design, the heater is placed on the same layer with the waveguide for fabrication compatibility with direct deposition of Si-Ge MLs and FLG. The spacing between the waveguide and the heater is chosen to be 1 µm. A conformal SiO2 cladding with thickness T1 = 0.4 µm is coated on the waveguide and the heater. The thickness of SiO2 buried oxide T3 is 2 µm. Several approaches are introduced to improve the TOPS performance. Si-Ge MLs and FLG can be subsequently deposited or transferred on SiO2 buried oxide. The number of FLG layers is chosen to be 15, which results in a thickness of ∼5 nm. The ML thickness T2 is set to 50 nm. Two air trenches can be etched on both sides of the waveguide-heater region as shown in Fig. 1(b). The width and depth (D1) of the air trenches are set to 1 µm and 2.4 µm, respectively. Specific device fabrication approach can be found in later section.
Fig. 1. (a) 3D illustration of the proposed TOPS. (b) The device cross-section (T1: SiO2 cladding thickness; T2: Si-Ge mutilayer thickness; T3: SiO2 buried oxide thickness; D1: air-trench depth). (c) Optical field distribution for TE mode. The width and height of Ge waveguide are 700 nm and 450 nm, respectively. (d) π-shift stationary thermal field distribution.
Two-dimensional finite element method (2D FEM) is used to simulate the performance of TOPSs [40]. We first conducted a mode analysis for the initial TOPS design. The refractive indices of Si, Ge, SiO2, Si-Ge MLs and air at 2 µm are 3.43, 4.02, 1.52, 3.72 and 1.00, respectively. Graphene has low light absorption for near-infrared light. According to the Pauli blocking effect, the Fermi level of graphene changes with the doping level. Graphene becomes transparent when the doping level is high enough [41]. The propagation loss is calculated to be ∼19 dB/cm when a gate voltage of 15 V is applied to the graphene according to [42]:
Stationary and time-dependent thermal simulations are conducted. The height and width of the 2D simulation area are 200 µm and 100 µm, respectively. The boundary conditions are set to be 293.15 K. The thermal conductivity in air, Ge, Si, Si-Ge MLs and SiO2 is 0.026, 60, 131, 0.3, 1.4 W/m·K, respectively [27,39]. Normally, a voltage is applied to the heater. When the current flows through the heater, Joule heat is generated and calculated from the material resistance of the metal. In the thermal simulations, a heater power of P is directly given to the Pt heater. The thermal simulation procedure is as follows:
- 1. A stationary thermal simulation is carried out and the heater power P is swept to obtain the cross-sectional temperature distribution profile.
- 2. The temperature profile is converted into the effective index and the phase shift is obtained from equation Δφ = 2πLΔneff/λ.
- 3. The result produced from Step 2 is fitted to retrieve Pπ. The heater is then set to this power, and then time-dependent thermal simulations are performed. The rising (τr) and falling (τf) time constants are defined as the time to vary between 10% to 90% of the largest phase variation of the TOPS (see Fig. 2), which can be extracted by tuning on and off the heater in the simulation. The time constant of the device is defined as the bigger (worse) value of rising and falling time constants, i.e., τ = max(τr, τf).
The design principle is straightforward: improving the thermal transfer to the waveguide and hindering the thermal leakage to the surrounding environment. Air trenches and Si-Ge MLs are introduced to provide thermal insulation. The weak thermal conductance G results in the decrease of Pπ according to Eq. (1). However, changes in G have opposite effects on Pπ and τ. The time constant τ increases as G decreases according to Eq. (2). Si-Ge MLs play a similar role to the undercuts in the TOPS design in Ref. [19], while preventing potential collapse of structures. To further reduce the time constant, a FLG layer is deposited on the Si-Ge MLs. The FLG layer is located directly under the heater and the waveguide, and its introduction enhances the heat transfer from the heater to the waveguide core. It is expected that the introduction of FLG would result in great reduction in the time constant, since the thermal conductivity in GeOI platform is weak.
In our design, the waveguide and the heater are surrounded by SiO2. Typically, air and SiO2 are both considered as low thermal conductivity materials, with the thermal conductivity of SiO2 about two orders of magnitude higher than air. Thus, the heat flows to the waveguide mainly through the SiO2. Without proper isolation underneath the waveguide, a large portion of heat would leak into the Si substrate. Figure 1(d) shows the steady-state temperature distribution. The heat is well confined in the vicinity of the waveguide-heater region thanks to the air trenches and Si-Ge MLs. According to Eq. (1), the thermal conductance G decreases when the heat is confined in a small region, which leads to the improvement in power efficiency.
3. Device optimization
The impact of the cladding thickness T1 on the performance of TOPSs is investigated with and without air trenches. Figure 3 shows Pπ, τ and FOM for different cladding thickness T1. Among them, TOPS designs in Figs. 3(a) and 2(b) have no air trench while TOPS designs in Figs. 3(c) and 2(d) have two air trenches with depth D1 = T1 + 2 µm. In both cases, Pπ increases slightly as the cladding thickness T1 increases from 0 to 0.4 µm, i.e., by 2.05% and 0.65% for TOPSs without and with air trenches, respectively. This can be explained by a slight increase of G when using a thicker SiO2 cladding, as most of the heat is transferred through the FLG. The time constant τ becomes much larger as T1 increases, indicating that the increase in the cladding thickness T1 has a greater influence on H than on G according to Eq. (2). That is because both the SiO2 cladding and the waveguide share the generated heat, and a thicker cladding layer results in an overall larger heat capacity of the heated region H, making the time constant increase. The time constant is a dominant factor, as the cladding thickness T1 changes, resulting in an almost linear increase in the FOM with T1. This means that the cladding thickness T1 should be reduced as much as possible to improve the performance of TOPSs. The FOMs without SiO2 cladding are 18.5 mW·µs and 9.5 mW·µs for TOPSs without and with air trenches, respectively. We note that, in practice, SiO2 cladding is often used to prevent contamination of the photonic chip. For optimized TOPS performance with air cladding, alternative packaging methods such as using a hermetic sealing cap can be implemented [43].
Fig. 3. Pπ, τ, and FOM for various cladding thickness when Si-Ge MLs thickness T2 is set to 50 nm. (a) Pπ, τ and (b) FOM for TOPS design without air trenches (a) Pπ, τ and (b) FOM for TOPS design with air trenches, air trench depth D1 is set to T1 + 2 µm.
Comparing results in Figs. 3(a) and 3(b) with Figs. 3(c) and 3(d), we note that adding air trenches can greatly improve the performance of TOPSs by a factor of 2. The impact of air trench depth D1 on the performance of TOPSs is studied in more details in Fig. 4. During the depth sweep, the cladding thickness T1 is set to 0, and the width of the air trenches is fixed to 1 µm. Structures with D1 from 0.1 µm to 2.0 µm are simulated. Increasing the air trench depth results in a rapid decrease in power consumption and a slight degradation of the time constant, and an overall improvement of the FOM. This is due to the decrease in G and H. The changing rate of Pπ and τ decreases as the depth increases to D1>1.5 µm, because the structures near the waveguide and the heater have the most influence on the temperature distribution due to their larger overlap to the thermal profile. When D1 equals 2 µm, Pπ and τ reach 4.6 mW and 2.1 µs, respectively. The simulation results indicate that air trenches with a depth of 1.5-2 µm are good enough, and further increasing the etching depth will not bring more benefits to the FOM.
Fig. 4. (a) Pπ, τ and (b) FOM of TOPS design with different air trench depth D1, the cladding thickness is set to 0 and the Si-Ge MLs thickness T2 is set to 50 nm.
The heat insulation is enhanced by introducing Si-Ge MLs under the waveguide and the heater. To investigate the influence of the Si-Ge MLs, the thickness T2 is swept from 0 to 200 nm in our simulation. Note that T2 = 0 means no Si-Ge MLs introduced. As shown in Fig. 5, both Pπ and τ decrease with T2 as a result of simultaneously reduced H and G in Eq. (2).
Fig. 5. Simulation results of (a) Pπ, τ and (b) FOM as a function of the Si-Ge MLs thickness T2, the cladding thickness is 0 and the air trench depth is 2 µm.
The overall FOM decreases from 9.5 mW·µs to 7.0 mW·µs, and the improvement becomes less for a larger T2 as τ reaches a limit of 1.8 µs at T2 = 200 nm. The introduction of Si-Ge MLs also shifts the guided modes towards the substrate, and the waveguide becomes more like a “ridge waveguide”, as shown in Fig. 6. As the thickness T2 increases, the mode overlaps more with the FLG and less with the waveguide sidewall, resulting in a slight increase in the propagation loss by 1.3 dB/cm for TOPSs with 200-nm Si-Ge MLs. Finally, the thickness of Si-Ge MLs is chosen to be 200 nm to avoid adding much to the waveguide loss. The resulting Pπ and τ reach 3.9 mW and 1.8 µs, with a FOM of 7.0 mW·µs. TOPS performance with and without graphene layer is also simulated. When air trench depth is 2 µm and Si-Ge MLs thickness is 200 nm, introducing 5-µm thick graphene reduces the time constant from 2.2 µs to 1.8 µs, marking a performance improvement of the TOPS by 15.5%. Compared to previously reported work with the largest experimental FOM value of 31 mW·µs [25], our design provides a promising approach to further improve the performance of the TOPS.
Fig. 6. TE mode for different T2 (a) 50 nm (b) 100 nm (c) 150 nm (d) 200 nm, T2 is the thickness of the Si-Ge MLs.
4. Discussion
A suggested fabrication process for the TOPS is discussed below. The process begins with a SOI wafer on which 2 µm thick Si is grown epitaxially. Then, 200 nm thick Si-Ge MLs are coated via a sputter-coating system [38]. Each layer has a thickness of ∼1 nm, which corresponds to a coating delay time of 30 s. After that, a 5 nm-thick FLG layer is prepared using chemical vapor deposition method and transferred onto Si-Ge MLs. Pt heaters are defined by lift-off process, and a thin dielectric layer of SiO2 or Al2O3 (∼30 nm) is then deposited on the FLG, e.g., through atomic layer deposition, to protect it from possible waveguide over-etching [44]. After that, the Ge waveguide will be deposited via low pressure chemical vapor deposition and patterned through dry etching. As a final step, two air trenches are created on both sides of the waveguide-heater region using a focused ion beam tool.
Si-Ge MLs are introduced due to their ultra-low thermal conductivity. We note that it is possible that the sputter-coating Si-Ge MLs have some wavy interfaces as shown in Ref. [39]. To improve the surface adherence to FLG, chemical mechanical planarization technique can be used to improve the surface quality of the Si-Ge MLs before the transfer of FLG. The Si-Ge MLs might introduce additional optical loss to the waveguide mode. To reduce the loss, fabrication efforts need to be devoted to improve the interface quality of the Si-Ge MLs, or thinner Si-Ge MLs can be adopted at the expense of the TOPS performance.
In practice, it is difficult to fabricate optical waveguides with strictly vertical sidewalls. We also provide analysis for the effect of waveguide sidewall angle on the device performance in Fig. 7, with air trench depth of 2 µm and Si-Ge MLs thickness of 50 nm considered. Both Pπ and τ stay almost constant when sidewall angle θ changes from 90° to 70°, resulting in a slight device FOM improvement of less than 1%.
Fig. 7. The effect of non-vertical sidewalls on the device performance. (a) Schematic showing the definition of the sidewall angle θ. (b) Pπ, τ and (c) FOM as a function of the sidewall angle.
5. Conclusion
In this paper, we have proposed a TOPS design in which a low power consumption of 3.9 mW and a fast thermal time constant of 1.8 µs can be potentially achieved, benefiting from the implementation of air trenches, Si-Ge MLs and FLG. The FOM is improved from 33.1 mW·µs to only 7.0 mW·µs. The proposed structure presents a new design approach for efficient and fast TOPSs and offers new opportunities for applications requiring large-scale device integration, such as optical phased arrays, photonic deep learning, and on-chip quantum simulation.
Funding
National Natural Science Foundation of China (61775164).
Acknowledgments
We acknowledge support by the Advanced Integrated Optoelectronics Facility at the Tianjin University.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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