1. Introduction

Recently, the rapid internet traffic growth has enabled a new wave of installation and upgrade of fiber access network like Fiber-to-the-Home (FTTH), where the 10-Gb/s class PON (passive optical network) deployment is ramping up steadily to replace the legacy GPON (Gigabyte PON). Moreover, new forms of high-speed network like the Fiber-to-the-Room (FTTR) [1], will further extend the reach of high-speed optical access from the home gateway to each room, mandating the deployment of plentiful of fiber optical links within the homes. Aiming at the consumer market for mass volume, low cost will be critical. Meanwhile, as the most cost-sensitive scenario in high-speed optical communication and after two decades of optimization, there isn’t much room to further exercise dramatic cost reduction in the fiber access network using PON transceivers. In this regard, new approaches with better cost structure are highly desired not only for FTTR, but also for the incoming fiber-to-everything paradigm shift.

As shown in Fig. 1(a), existing approaches in most PON transceivers employ two distinct wavelengths for transmitter (Tx) and receiver (Rx) paths to form a full-duplex optical transceiver. They mandate not only individual Tx and Rx optics, but also doubled optical alignment, bonding and packaging cost, contrasting the future economics appeal for mass volume. On the other hand, a single-wavelength half-duplex approach will be very attractive. By reusing the Tx and Rx optics, it has the potential to reduce the cost of optical transceiver roughly by a factor of two, as shown in Fig. 1(b). Importantly, the half-duplex optical transceiver should be able to provide high data rate as well as rapid reconfigurability to satisfy the need of future low-cost fiber access applications. So far, such a system hasn’t been demonstrated before, which is the goal of this work. Interestingly, this half-duplex optical transceiver will be in line with the half-duplex operation of the WIFI Accessing Point (AP) in each room of the FTTR network, meaning minimum or no real total bandwidth loss. Of course, the control and dispatch tend to be more complex, which will only add up to some change in the Media Access Control (MAC) chip and algorithm design with no substantial cost increase, since they don’t require new hardware or component.

 

Fig. 1. Optical transceivers realization schemes: (a) full-duplex and (b) half-duplex.

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2. Half-duplex optical transceiver

To make such a low-cost half-duplex optical transceiver with high speed and rapid reconfigurability, several requirements need to be met: a unified E/O-O/E device, individual biasing circuitry for Tx and Rx mode, a high-speed rapidly reconfigurable T/R switch, and preferably the integrated electronics. Let’s examine these factors one by one.

First, a unified E/O-O/E device is needed to serve as the bidirectional optical antenna to emitting or detecting light. For this optical antenna, one approach is to make a custom combo emitter-detector device [2–6]. However, not only the multimode operation limits the reach, its overall cost, performance and reliability render it not suitable for mass volume. In view of the fact that both the laser diode (LD) and the photodiode (PD) can be boiled down to a diode, forward or reverse biased, another approach is to explore the standard emitter device, e.g., laser, at its reverse/zero biased condition to fulfill the role of the PD, in which reasonable responsivity and bandwidth can be obtained [7–16]. Therefore, the dual-mode LD/PD approach is more preferred over others in the low-cost massive volume context.

Second, unlike the bidirectional passive RF antenna in wireless communication, the optical antenna, in this case the dual-mode LD/PD is an active device, which requires positive bias for Tx mode and negative bias for Rx mode. The simplest way is to use the bias tee to route Tx/Rx bias voltages [17–19]. The problem with this approach is that not only it’s bulky, but also in Rx mode a negative supply voltage needs to be provided, both contrasting the goal of low cost and high speed. Another approach is to use discrete switches, transistors, and amplifiers to constitute a dynamic biasing approach [16]. Although the bias tee is saved, the use of discrete devices limits the data rate as well as the reconfiguration time, and the cathode drive scheme in Tx mode mandates a supply voltage larger than standard supply voltage of 3.3 V, contrasting the low-cost initiative.

Third, the half-duplex operation requires a T/R switch to route the Tx and Rx signal paths at different time slots, which needs to not only pass high-speed multi-Gb/s signal, but also reconfigure itself rapidly. This suggests employing an integrated T/R switch over discrete components to meet these two requirements.

Finally, since the data rate and noise of the Rx electronics are very sensitive to its input parasitics, it should be placed in close proximity to the photodetector. With the required T/R switch before Rx for half-duplex operation, unless they are integrated together, the Rx performance will suffer. On the other hand, since the Tx LD driver sends large signal to drive the optics, the integration of the switch and the Tx LD driver is not mandatory.

Based on these observation and analysis, in this work, we have designed the first integrated cost-effective high-speed rapidly reconfigurable half-duplex optical transceiver front-end. It employs a Distributed-Feedback (DFB) LD as the optical antenna, dynamically biased as laser or photodetector and routed to Tx or Rx path by a custom-designed CMOS chip. Operating under the standard 3.3-V supply, the chip contains an integrated high-speed T/R switch, biasing circuitry for Rx and Tx modes, and a burst-mode transimpedance amplifier (BM-TIA). The high-speed T/R switch is able to route the multi-Gb/s signal as well as the individual bias for the dual-mode DFB-LD in Tx or Rx mode without a bias tee. The on-chip BM-TIA integrated with the T/R switch eliminates the local PD termination and reduce the Rx input parasitics that will otherwise degrade sensitivity and bandwidth. Thanks to this tight integration approach, 5-Gb/s transmission for both Rx and Tx have been achieved experimentally. Moreover, it can also reconfigure itself within 131 ns for rapid Tx-Rx and Rx-Tx mode switchover.

3. CMOS front-end chip

3.1 Transceiver architecture

Figure 2 shows the proposed half-duplex CMOS transceiver front-end chip connected with a DFB-LD. The T/R switch is realized in the form of the double-pole-double-throw (DPDT) switch, which is made of two single-pole-double-throw (SPDT) switches SPDT_A and SPDT_K to control the anode and cathode connection of the DFB separately. Shown in Fig. 2(a), in Tx mode, SPDT_A routes LD’s anode to the Tx LD driver’s input port (DRV_IN), and SPDT_K routes LD’s cathode to ground, forming positive LD biasing. The Tx LD driver is not integrated which doesn’t degrade the Tx performance, as mentioned before. Shown in Fig. 2(b), in Rx mode, SPDT_A routes LD’s anode to the on-chip BM-TIA and SPDT_K routes LD’s anode to the 3.3-V supply, constituting reverse LD biasing. The BM-TIA used here is modified from a prior design used in [20]. The bias current flow directions are annotated in both modes for clear illustration.

 

Fig. 2. Half-duplex optical transceiver front-end: (a) Tx mode; (b) Rx mode.

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The proposed half-duplex transceiver embodies all the necessary ingredients required: 1) The DFB-LD which acts as the unified O/E-E/O device is an off-the-shelf low-cost component; 2) The biasing circuitry which facilitates anode drive for both Tx and Rx modes is fully integrated on chip; 3) The on-chip T/R switch enables high-speed signal transmission as well as rapid reconfiguration; 4) The BM-TIA is integrated on chip to improve Rx performance; 5) The CMOS chip using a standard 3.3-V supply not only is cost effective, but also shows small footprint.

3.2 T/R switch design

The conceptual switch in Fig. 2 poses difficulties for CMOS realization, known for its capacity to integrate various functions into a monolithic electronic chip. Compared with the III-V technology, e.g., GaAs, InP, the core device performance in CMOS in terms of breakdown voltage and carrier mobility is relatively weak, which renders it challenging to make the T/R switch required here. In fact, the switch needs to interact with high-voltage signals from the LD driver side, which rules out the utilization of high-speed low-voltage CMOS device with breakdown voltage of less than 1 V. Moreover, as shown in Fig. 2, although in conceptual level Rx and Tx are isolated given the nature of SPDT, in practical implementation, they may be shortened together briefly in the mode transition period, damaging Rx electronics (BM-TIA) made with low-voltage device for high speed.

The design of the DPDT is detailed in Fig. 3(a). For SPDT_A connected with LD’s anode, based on the electrical operating voltages of TIA_OUT (∼ 0.6 V) and DRV_IN (∼ 2 V), the NMOS switch SPDT_A1 is used for the anode-TIA connection which routes low-voltage signal to the TIA made of low-voltage CMOS, while the PMOS switch SPDT_A2 is used for the anode-DRV_IN connection which routes high-voltage signal from the LD driver. The low-speed thick-oxide CMOS devices with higher breakdown voltages are used for safe operation, which will introduce more parasitic capacitance and potentially limit bandwidth.

 

Fig. 3. T/R switch details: (a) circuits, Rx path is marked red, Tx path is marked blue; (b) control timing.

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Therefore, the sizing of SPDT_A1 poses a design trade-off: a larger device reduces the switch’s ON resistance to lower its thermal noise contribution in Rx mode, which nevertheless shows larger capacitance and reduces the TIA bandwidth. The situation is further exacerbated by the fact that the reverse biased DFB-LD exhibits much larger capacitance than a typical PD at the same data rate. To compensate for the speed limitation from the large parasitics, an on-chip inductor L_A1 is placed between anode and SPDT_A1 to partially cancel the LD capacitance at high frequency to improve the TIA bandwidth. Meanwhile, large device size is also applied to SPDT_A2 switch to facilitate large current handling requirement (maximum 120 mA DC bias). Similarly, an on-chip inductor L_A2 is used to restore the Tx bandwidth as well.

Moreover, although Tx-Rx isolation is not a major concern for a half-duplex system, more decoupling capacitor is programed to connect to the gate of SPDT_A2 at its OFF state to minimize the potential Tx-to-Rx signal leakage which can easily overwrite the TIA input signal or even exceed the TIA overload limit to cause damage.

For SPDT_K, the PMOS switch SPDT_K1 is used to route the 3.3-V PD biasing, and the NMOS switch SPDT_K2 is used to route the LD ground biasing. Similar design practice in SPDT_A is exercised for their sizing. An on-chip power supply filter is integrated with the SPDK_K1 switch to realize low-noise power supply while providing good AC grounding.

As indicated before, the control timing of the T/R switch should be designed with caution. For SPDT_A, it’s critical to protect the low-voltage TIA circuits from being exposed to high voltages coming from the LD driver side. For SPDT_K, SPDT_K1 and SPDT_K2 should not be turned on simultaneously to avoid supply-ground short current which will damage SPDT_K1 and the 3.3 V supply filter made with relatively small current handling capacity of maximum 3 mA DC. Consequently, from Tx to Rx mode transition, Tx path is disconnected first, and Rx path is connected later. From Rx to Tx mode transition, Rx path is disconnected first, and Tx path is connected later. Moreover, high voltage is disconnected earlier than low voltage, while low voltage is connected earlier than high voltage. Following such operation guidelines, the resulted control timing of the T/R switch is shown in Fig. 3(b) with the ON/OFF sequence from (1)-(4), where high signal indicates ON and low signal indicates OFF, regardless of the NMOS/PMOS type. Both Rx-Tx and Tx-Rx switch transition time is designed to be less than 150 ns, ensuring fast T/R mode reconfiguration.

4. Experimental results and discussions

The transceiver front-end chip has been fabricated in a standard 40-nm CMOS technology and wired bonded to a 10-Gb/s DFB-LD used as the O/E-E/O device, as shown in Fig. 4(a). The operating wavelength is 1270 nm to be compatible with XGS-PON environment. The box-packaged device and its evaluation PCB is shown in Fig. 4. At 3.3-V reserve bias, the DFB’s responsivity is 0.3 A/W while the O/E bandwidth is around 3 GHz from measurement at 1270 nm.

 

Fig. 4. Half-duplex optical transceiver front-end: chip bonding detail and packaged device with its evaluation PCB.

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The switching performance of the T/R switch is shown in Fig. 5 by measuring the delay of the slowest bias volage node versus the switching control signal, based on the timing design in Fig. 3(b). From Rx to Tx mode, the anode biasing comes later, and the switching time is 131 ns as shown in Fig. 5(a). From Tx to Rx mode, the cathode biasing comes later, and the switching time is 98.9 ns as shown in Fig. 5(b). The fast switching ensures rapid Rx/Tx mode reconfiguration. The relative slower Rx to Tx transition is mainly due to the switching control generation from the timing circuit, where extra RC delay is used when turning on Tx switch to satisfy the timing sequence in Fig. 3(b).

 

Fig. 5. Switching delay: (a) Rx to Tx; (b) Tx to Rx.

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The transceiver performance for both Tx and Rx configuration are measured at 1270 nm, shown in Fig. 6. In Tx mode, an off-chip Bias-Tee is used to couple the DC bias current from a current source, and the AC modulation current from an electrical amplifier used as the laser driver. The DC bias current up to 120 mA has been used in the measurement without causing damage to the chip. The measured Tx output eye diagrams at 2.5 Gb/s and 5 Gb/s are shown in Fig. 5(a) and (b), where the speed is partially limited by the underestimated on-chip RC parasitics and the low-pass effect from PCB. The measured extinction ratios (ER) are 8.8 dB and 7 dB at 2.5 Gb/s and 5 Gb/s, respectively. In Rx mode, the receiver speed is also measured up to 5 Gb/s, shown in Fig. 5(c) and (d), which is mainly limited by the large parasitic capacitance from DFB-LD. Due to an instrument offset in the electrical channel of the oscilloscope, the Rx eye diagrams are squeezed to the upper side, which nevertheless are still wide open. The measured Rx sensitivity (average optical power: AOP) at BER of 1e-3 is -13.5 dBm at 5 Gb/s and -18.2 dBm at 2.5 Gb/s, which is partially limited by the large parasitics present in the input of the TIA.

 

Fig. 6. Transceiver measurement: (a) 2.5-Gb/s Tx eye; (b) 5-Gb/s Tx eye; (d) 2.5-Gb/s Rx eye; (d) 5-Gb/s Rx eye. The squeezed Rx eyes are due to an instrument offset in the electrical channel of the oscilloscope.

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Since the data rate of Rx and Tx have only reached 5 Gb/s in this work instead of the 10 Gb/s dictated in FTTR [1], further effort will focus on improving speed. For Tx, a major speed barrier tends to be the large parasitic capacitance from the switch designed with high-breakdown-voltage thick-oxide MOS with lower speed. Therefore, it’s possible to investigate switch design with thin-oxide MOS with low breakdown voltage to gain speed. Since the Tx driver’s voltage swing is doubled over the MOS’s safety operation region, a possible way is to stack multiple devices to collectively withstand the high voltage [21]. For Rx, the main speed limiter comes from the large parasitics of the DFB as well as the switch. In this case, more sophisticated bandwidth extension approach using inductor peaking network can be applied [22]. Going even beyond to 25 Gb/s and 50 Gb/s, except the aforementioned circuit design techniques, more advanced CMOS technology node, e.g., 28 nm and beyond may be required.

5. Conclusions

In the future fiber-to-everything world, cost reduction is essential. We have presented an integrated approach to make low-cost high-speed half-duplex optical transceiver with rapid reconfigurability, enabled by a custom-designed CMOS chip containing the T/R switch, the biasing circuitry, and a BM-TIA under the standard 3.3-V supply voltage. The transceiver can operate up to 5 Gb/s for both Tx and Rx configuration, while its reconfiguration time is less than 131 ns. To the authors’ knowledge, this is the first integrated cost-effective high-speed rapidly reconfigurable half-duplex optical transceiver front-end.