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Optical power degradation mechanisms in 271nm AlGaN-based deep ultraviolet light-emitting diodes

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Abstract

The degradation of AlGaN-based UVC LEDs under constant temperature and constant current stress for up to 500 hrs was analyzed in this work. During each degradation stage, the two-dimensional (2D) thermal distributions, I-V curves, optical powers, combining with focused ion beam and scanning electron microscope (FIB/SEM), were thoroughly tested and analyzed the properties and failure mechanisms of UVC LEDs. The results show that: 1) the opto-electrical characteristics measured before/during stress indicate that the increased leakage current and the generation of stress-induced defects increase the non-radiative recombination in the early stress stage, resulting in a decrease in optical power; 2) the increase of temperature caused by the deterioration of the Cr/Al layer of p-metal after 48 hrs of stress aggravates the optical power in UVC LEDs. The 2D thermal distribution in conjunction with FIB/SEM provide a fast and visual way to precisely locate and analyze the failure mechanisms of UVC LEDs.

© 2023 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement

1. Introduction

Deep ultraviolet light-emitting diodes (UVC LEDs) with the advantages of small size, low power consumption, and environmental friendliness [13] are considered a substitute for an ultraviolet mercury lamp in terms of sterilization, and disinfection. In addition, UVC LEDs have also gained widespread interest due to their wide applications in communication sensing [4], phototherapy, and UV curing [5]. Despite technological developments, UVC LEDs continue to have low optical output power. On one hand, the relatively low conductivities of n- and p-type AlGaN layers, combining with high contact resistances at high Al mole fractions result in high operating voltages in UVC LEDs and joule heating of the device. In addition, more thread dislocations (TDs), point defects, defect complexes, and impurities will be introduced in Al(Ga)N with a high Al component, which considerably enhances the non-radiative recombination [6]. Furthermore, the strong transverse magnetic (TM)-polarized anisotropic emission, which can be easily trapped, became dominant as the Al mole fraction in the active region increased [710]. On the other hand, the large refractive index difference between AlGaN layers and air reduces light extraction efficiency (LEE) and the light output. Many efforts have been reported to improve the optical efficiency and reliability of UVC LEDs. In general, three primary approaches have been adopted to improve the quantum efficiency of UV LEDs. The first method is to enhance internal quantum efficiency (IQE) by growing low-defect-density AlN templates on sapphire substrates to reduce defects and dislocation density and then improve radiative efficiency [1113]. The second is to optimize the quantum well structure to limit carrier leakage or improve n- and p-type doping to reduce operating voltage and increase carrier injection efficiency [14,15]. The third one is to increase the photon extraction efficiency by shaping UVC LEDs and patterning their substrates to improve LEE, such as high-reflectance metals, reflective photonic crystals (PCs), and patterned nano-structures, have been explored [1618]. Simultaneously, various new device structures have been proposed to improve their efficiency and stability while making the radiation wavelength move to the deep UV, such as core-shell structure [19], quantum dot structures [20], and nanorods [21].

Currently, UVC LEDs suffer low optical power and rapid degradation, resulting in a lifetime only about 10,000 hours at room temperature. The reliability of UVC LEDs has been extensively studied [2225]. Meneghini et al. describe an analysis that the degradation of UVC LEDs has been attributed to the generation/propagation of defects in the active region, resulting in an increase of the non-radiative recombination rate [26]. In UVB and UVC LEDs, point defects, particularly impurities, and the accumulation of charges at heterointerfaces reduce the carrier injection efficiency, resulting in a decrease in the optical power [27]. In addition, the thermal performance of UVC LEDs is crucial for achieving its high power output. However, there are limited studies on the thermal properties of UVC LEDs due to instrument limitations. For example, the resolution of infrared thermal imager is relatively low, and the thermal distribution based on hyperspectral imaging technology can only be applied to visible light [28].

We prepared AlGaN-based UVC LEDs on an AlN/sapphire template and investigated their thermal distributions under constant DC current and temperature stress. The 2D thermal distributions of the UVC LEDs under test were obtained by a microscopic thermoreflectance imaging system. The temperature variations were linked to degradations in the metal structures of UVC LEDs. The results show that the Cr/Al layer of p-metal of UVC LEDs fracture during the operation, which increases the self-heating of the device and negatively impacts its optical output.

2. Device fabrication and characterizations

The schematic diagram of the commercial UVC LEDs used in this study is shown in Fig. 1(a). The wafer was grown on a (0001)-oriented sapphire template using metal-organic chemical vapor deposition (MOCVD). The UVC LED chip structure consists of, from top to bottom, a passivation layer, a p-metal layer, an indium tin oxide (ITO) layer, an n-metal layer, epitaxial layers, and substrate. The n- and p-type dopants are Si and Mg, respectively. A Mg-doped p-type electron blocking layer (EBL) was deposited in the active region to prevent electron overflow. An “E” shaped mesa was prepared by ICP etching, and a transparent ITO layer was deposited on p-GaN to achieve better ohmic contact. Ti/Al/Ti/Pt and Cr/Al/Ni/Pt/Au/Ti were used for the n and p ohmic contacts and current spreading, respectively, followed by a passivation layer and a metal support layer. The bottom view of the UVC LED when it is powered on is captured from the sapphire side by a camera and shown in Fig. 1(b).

 figure: Fig. 1.

Fig. 1. (a) Schematic diagram of the UVC LED. (b) The bottom view (from substrate to metal-2) image when the UVC LED is lit.

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The size of the chip is 500 × 500 µm2. After the sapphire substrate is thinned, the wafer is split by laser, and then broken into chips. The chip was flip-fixed to a gold-plated ceramic bracket, which was solder on a square aluminum plate. The aluminum plate was mounted on a temperature controller during the measurement or stress operation. To ensure the reliability of the experiments, 10 samples from the same wafer with a peak wavelength of 271 nm were used, and the average optical output power and average forward voltage at an operating current of 100 mA are 12 mW and 5.8 V, respectively.

The samples were driven at a DC current of 100 mA, with the heat sink temperature controlled at 50°C for stress operation. The UVC LEDs underwent 500 hrs at most in aging test. At each stage of stress (0 hr, 24 hrs, 48 hrs, 96 hrs, 168 hrs, 256 hrs, and 500 hrs), we tested the 2D thermal distributions, the I-V curves and the optical powers of the samples. When the thermal distributions of the samples changed significantly under a certain stress stage, we removed one sample from the aluminum plate to analyze its internal cross-sectional structure of electrodes by focused ion beam and scanning electron microscope (FIB/SEM) (Thermo Fisher Scientific Inc., Helios).

I-V curves are measured using a source meter (Keithley 2611). The variation of optical powers and voltages are measured by an aging test machine (Wei Min Industrial Co., Ltd. LED-800). The microscopic thermoreflectance imaging system mainly consists of a camera (HK-A1281-CC500/CM500), a microscope, an incident red LED, temperature controllers (Arroyo Instruments 5305), and source meters (KeySight B2911A, Yokogawa GS610). The micro-scopic thermoreflectance imaging system is based on the principle that the reflectance of material surface is proportional to the change in temperature, and the reflectance is proportional to the intensity of the reflected light [29,30], as shown in Eq. (1) and Eq. (2):

$$L(T )= L({{T_0}} )+ \frac{{dL}}{{dT}}({T - {T_0}} )$$
$$T \approx {T_0} + \frac{{dT}}{{dL}}[{L(T )- L({{T_0}} )} ]\approx {T_0} + {K_L}\Delta L$$
Where T is the temperature of LED and KL is the temperature sensitive parameter (TSP), L(T) and L(T0) are the reflected light intensity at temperature T and T0, respectively, while ΔL is the relative difference of reflected light intensity. The temperature can be calculated by fitting KL.

3. Results and discussions

The normalized optical powers of five representative samples acquired at 100 mA and 25°C heat sink temperature after each stress stage are shown in Fig. 2(a) as a function of operation time, with all values normalized to the original values before stress. Some samples were removed for FIB/SEM testing after each stress stage, so only the remaining five samples are shown here. The same trend was observed for the other five samples. The illustration shows the chip exhibits significant optical power degradation, especially in the first 96 hrs of operation. The average optical powers for 24 hrs, 48 hrs and 96 hrs droop to 79%, 68%, and 63%, respectively. After 96 hrs, the optical power drop slowed down, and by 500 hrs, the optical power had dropped below 50%.

 figure: Fig. 2.

Fig. 2. (a) The optical power of UVC LEDs labeled 1, 2, 3, 4, and 5 varies with the operation time under stress of 100 mA and 50°C, and the optical power is normalized to the original value before stress. (b) I-V curves of UVC LEDs after different operation times.

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The I-V curves at 25°C heat sink temperature under different operation times are shown in Fig. 2(b). The left Y-axis represents the leakage current when the voltage is less than 0, while the right Y-axis, plotted logarithmically, corresponds to the forward current when the voltage is greater than 0. It is evident that the leakage current of UVC LEDs increases with operation time, especially within the 48 hrs. This phenomenon is consistent with previous studies [26,31]. The increased leakage current and stress-induced defects generation increase the tunneling and non-radiative recombination paths in the active layer, leading to a decrease in optical power. For further insight, we presented the variation of LED forward voltage at 1 µA (Fig. 3(a)) and 100 mA (Fig. 3(b)) as a function of operation time. From Fig. 3(a) and Fig. 2(a), it can be observed that the optical power and voltage vary with similar trends, indicating a correlation between optical and electrical degradation of the samples. At the high-injection current (Fig. 3(b)), the decrease of the voltage within the first 96 hrs may be due to the decreased resistivity of the p-type material and/or the resistance of the non-ideal (i.e., partial Schottky type) p-contact. Afterwards, the voltage increases gradually, indicating a change in electrode structure [32].

 figure: Fig. 3.

Fig. 3. The voltage of different chips varies with operation time with current at (a) 1µA and (b) 100 mA.

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The 2D thermal distributions of all samples at different operation times are displayed in Fig. 4(a)-(g). The size of the intercepted picture is 137 × 135 pixels, and only the thermal distributions at 100 mA are presented here. During the first 24 hrs of stress, the temperature at the interface of cathode and anode (as indicated by the white rectangular area in Fig. 4(b) and black arrows in Fig. 1(a)) was higher than those at other locations due to the relatively large ohmic contact. In contrast, the temperature at the p-side remained almost constant. After 48 hrs, the temperature distributions began to change in the opposite direction. The temperature at the p-side increased rapidly with operation time and eventually spread to the n-side as the operation time approached 500 hrs. This resulted in a high temperature throughout the entire chip.

 figure: Fig. 4.

Fig. 4. (a)-(g) 2D thermal distribution changes with operation time (0 hr, 24 hrs, 48 hrs, 96 hrs, 168 hrs, 256 hrs, 500 hrs, respectively). The captured image is 137 × 135 pixels. (h) The average temperature of all samples varies with operation time.

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Figure 4(h) illustrates how the average temperature changes across the chip surface as the operation time increases. The average temperature increases with the operation time, especially at the 48-hour mark. The temperature rise can lead to an increase in non-radiative recombina-tion, which may further aggravate the optical power [33,34]. Additionally, an increase in non-radiative recombination centers can lead to an increase in reverse bias current [35]. Hence, temperature rise may exacerbate the optical power and increase the reverse bias current. In order to compare the temperature difference between n- and p-side, we obtained the data from two rectangular areas (marked in Fig. 4(a)), representing the n- and p-side on the right and left, respectively. We plotted the temperature variation of the two areas with the operation time, as shown in Fig. 5. Prior to 24 hrs, the temperature of n-side was slightly higher than that of p-side. However, as the duration of the stress persisted, the temperature of p-side increased rapidly, and ultimately becoming higher than that of n-side.

 figure: Fig. 5.

Fig. 5. The temperature of n- and p-side varies with operation time. The location of the intercepted area is shown in Fig. 4(a), where the left rectangle is the position of p-side, and the right rectangle denotes n-side.

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To investigate the degradation mechanism, we used FIB/SEM to perform cross-sectional structural analysis on the electrode. According to the thermal distributions of samples, the cutting points were located in p-side, n-side, and the positions between them, respectively. The variations of the cross-sectional structure of n-side with operation time are depicted in Fig. 6(a)-(f). We have marked the positions of the passivation layer, the Au layer and the n-metal layer in the diagram. During the initial stages, small defects (indicated by red circles) are observed on the n-side, which are close to n-metal and are likely caused by the deficiencies in the deposition process of the underlying p-metal. Upon further analysis, we identified these defects as being located in the Cr and Al layers, which are not uniformly deposited. These small voids may have contributed to the high temperature observed on n-side during the early stages of stress. In the later stage of stress, the structure of n-side remains relatively stable with minimal changes compared to the p-side. Small defects are not observed in the images taken after 48 hrs of stress because they are captured from different chips. After 96 hrs of stress, the rising temperatures may have been caused by the transfer of heat from the p-side to the n-side.

 figure: Fig. 6.

Fig. 6. (a)-(f) are the FIB/SEM views of the n-side of the samples with stresses of 0 hr, 24 hrs, 48 hrs, 96 hrs, 168 hrs and 256 hrs, respectively. The red circle shows small defects.

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Figure 7(a)-(f) demonstrate the cross-sectional structure variations of the p-side edge and internal regions. We have marked the positions of the passivation layer, the Au layer and the ITO layer in the diagram. Within 24 hrs of stress, defects are also found on the p-side, near the ITO (white slender line). These defects are all located in the bottom metal (Cr/Al) layer of p-metal, as shown by comparing Fig. 6 and Fig. 7. After 48 hrs of stress, the defects gradually increase on both the edge and inside of the p-side. The deterioration is more obvious after 96 hrs of stress, resulting in a fracture width of approximate 2 µm at 256 hr. The changes in the n- and p-side structure correspond to the temperature distribution variations as shown in Fig. 4. After 48 hrs of stress, the Cr/Al layer of p-metal, acting as ohmic contact and current spreading, begins to deteriorate. As shown in Fig. 3(b), the voltage drop in the early stress stage likely indicates an improvement in the ohmic contact. Therefore, we believe that the metal layer crack does not exist throughout the entire p-side, i.e., some regions are still in contact with ITO and the deterioration of the p-metal layer doesn’t significantly result in voltage change but increases temperature. However, after 96 hrs of stress, the continuous deterioration of p-metal further exacerbates the ohmic contact and current crowding and leads to rise in chip temperature [36]. By comparing the UVC thermal distribution changes and the FIB/SEM results, we conclude that defects in the underlying metal (Cr/Al) of p-metal occur during the fabrication process and are constantly expanded by stress. Consequently, the temperature of the p-side gradually increases during the operation time, exacerbating the optical power and the reverse leakage current of UVC LEDs.

 figure: Fig. 7.

Fig. 7. FIB/SEM views of the p-side. (a)-(f) are the FIB/SEM views of the p-side of the samples with stresses of 0 hr, 24 hrs, 48 hrs, 96 hrs, 168 hrs and 256 hrs, respectively. The red circle shows small defects.

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4. Conclusion

We used a combination of techniques, including the 2D thermal distribution technique, focused ion beam combined with scanning electron microscope (FIB/SEM), and electroluminescence (EL) to investigate the failure mechanisms of 271 nm AlGaN-based UVC LEDs. Our results show that this approach provides a fast and visual way to precisely locate and analyze the failure mechanisms of UVC LEDs. In the early stress stage, the drop of optical power may be attributed to increased leakage current and non-radiative recombination by stress-induced defects. After 48 hrs of stress, the gradual failure of the underlying metal (Cr/Al) structure of p-metal leads to an increase of temperature of UVC LEDs and eventually results in a high temperature throughout the entire chip, while the n-side contact of UVC LEDs remains stable during the operation time. Therefore, the primary objective to achieve longer-life UVC LEDs is to improve the properties of the underlying metal of p-metal in the fabrication process. This can be accomplished by improving the parameters in the metal process, changing the order of the metal layers, optimizing more suitable metal thicknesses, or finding other metal replacements.

Funding

National Natural Science Foundation of China (62274138, 62275227); Major Science and Technology Project of Fujian Province (2020H6017, 2022H6004); Natural Science Foundation of Fujian Province (2019J05022).

Disclosures

The authors declare no conflicts of interest.

Data availability

Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.

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Data availability

Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.

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Figures (7)

Fig. 1.
Fig. 1. (a) Schematic diagram of the UVC LED. (b) The bottom view (from substrate to metal-2) image when the UVC LED is lit.
Fig. 2.
Fig. 2. (a) The optical power of UVC LEDs labeled 1, 2, 3, 4, and 5 varies with the operation time under stress of 100 mA and 50°C, and the optical power is normalized to the original value before stress. (b) I-V curves of UVC LEDs after different operation times.
Fig. 3.
Fig. 3. The voltage of different chips varies with operation time with current at (a) 1µA and (b) 100 mA.
Fig. 4.
Fig. 4. (a)-(g) 2D thermal distribution changes with operation time (0 hr, 24 hrs, 48 hrs, 96 hrs, 168 hrs, 256 hrs, 500 hrs, respectively). The captured image is 137 × 135 pixels. (h) The average temperature of all samples varies with operation time.
Fig. 5.
Fig. 5. The temperature of n- and p-side varies with operation time. The location of the intercepted area is shown in Fig. 4(a), where the left rectangle is the position of p-side, and the right rectangle denotes n-side.
Fig. 6.
Fig. 6. (a)-(f) are the FIB/SEM views of the n-side of the samples with stresses of 0 hr, 24 hrs, 48 hrs, 96 hrs, 168 hrs and 256 hrs, respectively. The red circle shows small defects.
Fig. 7.
Fig. 7. FIB/SEM views of the p-side. (a)-(f) are the FIB/SEM views of the p-side of the samples with stresses of 0 hr, 24 hrs, 48 hrs, 96 hrs, 168 hrs and 256 hrs, respectively. The red circle shows small defects.

Equations (2)

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L ( T ) = L ( T 0 ) + d L d T ( T T 0 )
T T 0 + d T d L [ L ( T ) L ( T 0 ) ] T 0 + K L Δ L
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