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Abstract
Ultra-compact waveguide crossing (UC-WC) is a basic component in optoelectronic fusion chip solutions, as its footprint is smaller in the orders of magnitude than that of traditional photonic integrated circuits (PICs). However, a large loss of UC-WC (decibel level) becomes a barrier to scaling and practicality. Here, we propose a series of ultra-low loss UC-WC silicon devices using an advanced hybrid design that combines the adjoint method with the direct binary search (DBS) algorithm. Simulation results show that our 2 × 2 UC-WC has an insertion loss as low as 0.04 dB at 1550 nm, which is about ten times lower than the previous UC-WC results. In the valuable C-band (1530–1565 nm), the insertion loss of UC-WC is lower than -0.05 dB, and the channel crosstalk is lower than -34 dB. Furthermore, for the 3 × 3 UC-WC device, the highest insertion loss in the entire C-band is approximately -0.07 dB, and the highest channel crosstalk is lower than -33 dB. Additionally, the 4 × 4 and more complex 8 × 8 UC-WC devices were also analyzed. The highest insertion loss for 4 × 4 and 8 × 8 UC-WC in the C-band is only -0.19 dB and -0.20 dB, respectively, and the highest channel crosstalk is approximately -22dB and -28 dB, respectively. These results confirm that the designed devices possess two attractive features simultaneously: ultra-compactness and ultra-low insertion loss, which may be of great value in future large-scale optoelectronic fusion chips.
© 2022 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
In the modern information society, the demand for computational resources has increased dramatically, and the density of traditional integrated circuit transistors is approaching the physical limit. In this regard, photonic integrated circuits (PICs) fabricated on silicon-on-insulator (SOI) substrates have been extensively studied owing to their high transmission efficiency, low power consumption, strong integration, and compatibility with complementary metal-oxide-semiconductor processes. Ultra-compact waveguide crossing (UC-WC) on SOI is an important device unit to form optical switches [1,2] and optical routers [3,4]. A variety of implementation schemes for waveguide crossing have been reported as follows: 1) Shaped taper waveguide crossing [5,6], a device with a footprint of 6µm × 6µm, was reported in Ref. [5], its insertion loss and crosstalk are -0.16dB and -40dB, respectively. 2) Multimode interferometers (MMIs) [7–9], waveguide crossing reported in Ref. [7] with a combination of an MMI and a mode division multiplexer (MDM), have a footprint of 34µm × 34µm, an insertion loss of -0.9dB, and a crosstalk of -24dB. 3) Photonic-crystal-like (PhC-like) subwavelength structures [10,11], in Ref. [11], based on photonic crystals waveguides, 4 × 4, 5 × 5, and 6 × 6 star-shaped waveguide crossing devices were realized in a 60nm bandwidth with a center wavelength of 1550nm. Their insertion losses are -0.75, -0.9dB, and -1.5dB, respectively, and their crosstalks are -22.5, -20, and -18dB, respectively.
Most of the solutions above adopted “cross-shaped waveguide crossing”, and the problems of high insertion loss or large size accompanied them. The realization of ultra-low loss and ultra-compact “multichannel waveguide crossing” on the SOI platform is also of great significance for the implementation of truly high-density PICs in the future. In recent years, the use of inverse design methods to design photonic devices has been extensively reported. In traditional design methods, the design space of the device is fixed to a few parameters, which are highly dependent on the domain knowledge and experience of the designer. However, inverse design includes heuristic algorithms, which expands the design space and automatically finds excellent parameter combinations. Many photonic devices have been designed using the inverse design method, such as wavelength demultiplexer [12,13], power beam splitter [14,15], and mode converter [16]. Furthermore, many intelligent optimization algorithms are applied to inverse design, including genetic algorithm [17], deep learning [18,19], direct binary search (DBS) algorithm [20–22], objective-first method [23,24], and adjoint method [25–27]. However, the multichannel waveguide crossing devices reported so far remain unsuitable for practical applications owing to their high insertion loss. For example, in Ref. [28], such a 3 × 3 device has high insertion losses to each output channel of -3.22, -2.1, and -1.73dB (corresponding to transmittances of 47.6%, 61.8%, 67.2%, respectively). Excessively high loss hinders their application to future optoelectronic integrated circuits.
Here, we propose a new design method with excellent optimization ability, and use it implement a series of ultra-low insertion loss UC-WC devices in the C-band. Such ultra-low loss UC-WC devices are urgently needed at present, and we believe that our design method and devices will be applied to future optoelectronic fusion schemes. In this paper, the details of our design method are presented in Section 2; The structure and performance of the designed UC-WC are analyzed in Section 3; Finally, the full text is summarized in Section 4.
2. Chip design
Figure 1 shows a possible schematic of a future optoelectronic fusion chip and our 2 × 2 UC-WC device. Figure 1(a) is a schematic diagram of a possible optoelectronic fusion chip composed of PICs and EICs. Figure 1(b) is a schematic diagram of a traditional photonic device microring and scattering unit designed by the inverse design method. The size of a single device in EICs is usually several micrometers. In contrast, the size of a traditional microring is usually hundreds of micrometers, which is two orders of magnitude larger than that of EICs. Thus, the size is a major barrier to optoelectronic fusion. Photonic devices designed using inverse design methods are only a few micrometers in size, which alleviates the aforementioned problem. Figure 1(c) and Fig. 1(d) are schematic diagrams of our 2 × 2 UC-WC designed by DBS and hybrid phased optimization (HPO), respectively. Simulation results show that the devices designed with the HPO method have considerably lower insertion losses than the DBS devices. Only when the insertion loss is sufficiently low, real large-scale integration can be realized. Further, only with ultra-small size, optoelectronic integration can be truly achieved.
Fig. 1. Schematic diagram of an optoelectronic fusion chip and a 2 × 2 UC-WC device. (a) Schematic diagram of a possible optoelectronic fusion chip. (b) Schematic of a microring and a 2 × 2 UC-WC. (c) 3D schematic diagram of a 2 × 2 device and the structure designed by DBS. (d) Top view of a 2 × 2 device and the structure designed by HPO.
Our 2 × 2 device consists of two input waveguides, two output waveguides, and a design area. The widths of the input and output waveguides are both set to 500nm, the distance between the upper and lower waveguides is 2µm, and the size of the design area is 4µm × 3µm. We divide the design area into 200 × 150 pixels of 20nm × 20nm. The design goal is to make the input of IN1 with an output from OUT2 as high as possible and the input of IN2 with an output from OUT1. Here, we first use the adjoint method to optimize the design area and then use the DBS algorithm to iterate the obtained results further. The design method flowchart is shown in Fig. 2.
The adjoint method [29] is a method for solving physical problems with topology optimization. It has been widely used in industrial models since it was proposed [30–32] and has also been widely used in the design of photonic devices in recent years. DBS was first proposed in [33] for holographic optical design and began to be used in silicon photonic device design in [34,35]. The advantage of DBS algorithm is simplicity, easy implementation, and fast convergence speed. The HPO procedure includes the adjoint method combined with DBS and is divided into three stages. The first stage is the permittivity grayscale stage; the second stage is the permittivity binarization stage. The first two stages are performed using the adjoint method. The third stage is to use DBS for additional local search of the existing structure to find a better structure.
In the permittivity grayscale stage, the permittivity ɛ of each pixel in the design area can have any value between the background permittivity ɛb and the material permittivity ɛm. Now, as the variable ɛ is continuous, we can optimize with gradients. In general, to calculate the gradient of the figure of merit (FOM) with respect to the permittivity ɛ, each pixel should be perturbed to calculate the gradient as shown in Eq. (1):
This requires a computational complexity of O(n), and the computational cost will be too large. The adjoint method only needs to perform a forward simulation and an additional adjoint simulation for a total of two simulations. Subsequently, the global gradient information in the current situation can be obtained (Eq. (2)), and the computational complexity becomes O(1). FOM can be viewed as a function of electric field and permittivity, and the electric field in turn is a variable related to permittivity.
Herein, the first term on the right side of Eq. (2) can be obtained by the adjoint method [27] as Eq. (3):
In the permittivity grayscale stage, the FOM will rise until convergence. At this time, the permittivity ɛ is distributed in the interval [ɛb, ɛm], the device cannot be manufactured. Therefore, we need the permittivity binarization [36,37] stage to binarize the permittivity ɛ to ɛb or ɛm, the main method used for binarization is projection [36,38]. Before projection, the permittivity ɛ ∈ [ɛb, ɛm] is normalized to ɛ ∈ [39,1], and the projection formula is as follows:
The transition from the grayscale stage to the binarization stage will lead to the performance degradation inevitably. Therefore, we use the DBS algorithm with excellent local optimization ability to further improve the device performance. At the DBS stage, we further optimize the 200 × 150 pixels in the design area. However, for optimizing a single pixel, 30,000 simulations are required, which is too computationally expensive. Thus, we use the original adjacent 5 × 5 array of pixels as a new pixel in DBS. The new pixel size is 100nm × 100nm, and there are 40 × 30 pixels in total. Each new pixel is calculated once for all ‘0’ and all ‘1’, and the structure with the highest FOM is kept. As a result, we only need 2400 simulations. Integrating small pixels into large pixels not only saves computational resources but also prevents the generation of too small hole structure to manufacture. Additionally, for the N × N device, the FOM used in optimization process is defined as follows:
Where the Pij is the energy intensity which input from input channel i and output from output channel j. Among them, i = 1, 2… N-1, N, and j is the target output port j corresponding to the input port i. The FOM is the sum of output energy intensity of each target channel.In our device design, our background is air, and the material is silicon, so ɛb is ɛair = 1, and ɛm is ɛSi = 3.482≈12.11. Here, we use the general insertion loss (IL) and crosstalk (CT) to evaluate the performance of our devices. Insertion loss is an important indicator for evaluating optical devices because only when the loss is sufficiently small, it can be applied to future PICs. Insertion loss is defined as follow:
where Pout and Pin are the energy intensities of the target output port and input port, respectively. Similarly, the crosstalk is defined as follow: where Pout and Pin are the energy intensities of the nontarget output port and input port, respectively.3. Simulation and results
To demonstrate the superior performance of our HPO-designed UC-WC device, we design the same device using the DBS algorithm and compare the performance. All simulations in this study were performed on FDTD analysis software (Ansys Lumerical FDTD). As the DBS algorithm is sensitive to the initial structure [40], we empirically give a suitable initial structure for each device (each input port is connected to the desired output port with silicon, and the other areas are air). The initial structure of HPO is set such that the value of each pixel is (ɛair+ɛSi)/2.
Figure 3 shows the structure, light field, and optimization iterative process diagrams of the 2 × 2 devices designed with the DBS algorithm and HPO, and its size is 4µm × 3µm. Figure 3(a–d) on the left show the results of the DBS algorithm, and Figs. 3(e–h) on the right show the results of the HPO method. Figure 3(a) and Fig. 3(e) depict the refractive index distribution structures of the devices designed by DBS and HPO, respectively. Figure 3(b), Fig. 3(c) and Fig. 3(f), Fig. 3(g) are the light field distribution diagrams of the devices designed by DBS and HPO at 1550 nm, respectively, when the input channels are IN1 and IN2. Figure 3(d) and Fig. 3(h) are the insertion losses versus iteration number of the 2 × 2 devices designed by DBS and HPO, respectively. It can be seen that the insertion loss of the device designed by the DBS method is gradually reduced during the entire optimization process until convergence. In contrast, for HPO, the performance of the device is rapidly improved; that is, the insertion loss is rapidly reduced because the optimization is based on gradients in the grayscale stage. In the final stage, the DBS method is used to search further for a better structure to improve the device performance. At this stage, we calculate each pixel in the structure once, which requires 40 × 30 iterations. Compared with the two methods, our HPO method not only has fewer computations than the DBS method but also yields better device performance and lower insertion loss.
Fig. 3. Comparison of 2 × 2 devices designed by the DBS and HPO. (a) Device structure designed by DBS. (b)-(c) Light field distributions of the DBS device. (d) Insertion loss of the DBS device with respect to the number of iterations. (e) Device structure designed by HPO. (f)-(g) Light field distributions of the HPO device. (h) Insertion loss of the HPO device with respect to the number of iterations.
Figure 4 shows the performance of the device designed by our two methods. Figure 4(a–c) and Fig. 4(e–g) are the light field distributions of the two devices under light sources of 1530, 1545, and 1565nm, respectively, when the input channel is IN1. It can be seen that the light intensity distribution of the DBS device in the white box is different under different wavelength light sources. In contrast, for our HPO device, in the 1530–1565nm band, the light fields are highly consistent, which further demonstrates the stability of our device. Consequently, this wavelength-insensitive waveguide crossing device in the C-band is well suited for future applications in real PICs. Figure 4(d) is the insertion loss of the device designed by DBS when the input channels are IN1 and IN2 and the output channels are OUT2 and OUT1, represented by T12 and T21, respectively. The insertion loss curves of subsequent devices are also shown. That is, Tij represents the insertion loss curve from channel i input and channel j output. It can be seen that, in the entire C-band, the highest insertion loss of the device designed by the DBS algorithm is -0.44dB, and the highest crosstalk is -26dB. Figure 4(h) is the insertion loss curve of the HPO device. At this time, at 1550nm, the insertion loss is -0.04dB, and in the C-band, the insertion loss is lower than -0.05dB, and the crosstalk is lower than -34dB. Comparing the two devices designed by DBS and HPO, the HPO method reduces the insertion loss from -0.44dB (DBS device) to -0.05dB (HPO device), and the crosstalk from -26dB to -34dB, which greatly improves the performance.
Fig. 4. Light fields of different wavelengths and insertion loss curves of two devices. (a-c) Light field diagrams of the DBS device under 1530, 1545, and 1565nm light sources. (d) Insertion loss curve of the DBS device. (e-g) Light field diagrams of the HPO device under 1530, 1545, and 1565nm light sources. (h) Insertion loss curve of the HPO device.
Figure 5 shows the structure and performance of our designed 3 × 3 device with the DBS algorithm and HPO (size: 4µm × 3µm). Among them, Fig. 5(a–f) on the left are the results of the DBS algorithm, and Fig. 5(g–l) on the right are the results of the HPO method. Figure 5(a) and Fig. 5(g) show the refractive index distribution structures of the DBS-designed and HPO-designed devices, respectively. Figure 5(b) and Fig. 5(h) are the insertion loss curves of the 3 × 3 DBS device and HPO device versus the number of iterations, respectively. Figure 5(c) and Fig. 5(i) are the insertion losses of the two devices, respectively, when the input channels are IN1, IN2 and IN3 and the output channels are OUT3, OUT1 and OUT2, represented by T13, T21 and T32, respectively. From the calculation, in the entire C-band, the highest insertion loss among the three channels of the device designed using the DBS algorithm is -0.93dB, and the highest crosstalk is -20dB. In contrast, for the HPO device in the C-band, the highest insertion loss among the three channels is -0.07 dB, and the highest crosstalk is -33dB. Comparing the two UC-WC devices designed by DBS and HPO, the HPO method reduces the insertion loss from -0.93dB (DBS-designed device) to -0.07dB (HPO-designed device), and the crosstalk from -20dB to -33dB. Figure 5(d–f) and Fig. 5(j–l) are the light field distribution diagrams of the DBS-designed device and HPO-designed device at 1550nm, respectively, when the input channels are IN1, IN2 and IN3.
Fig. 5. Structure and performance of 3 × 3 devices designed by DBS and HPO. (a) Device structure optimized by DBS. (b) Insertion loss of the DBS device with respect to the number of iterations. (c) Insertion loss curve of the DBS device. (d)-(f) Light field distributions of the DBS device. (g) Device structure optimized by HPO. (h) Insertion loss of the HPO device with respect to the number of iterations. (i) Insertion loss curve of the HPO device. (j)-(l) Light field distributions of the HPO device.
Figure 6 shows the structure, light field, and optimization iterative process diagrams of the 4 × 4 devices designed by the DBS algorithm and HPO. Both devices have a size of 4µm × 4µm. Figure 6(a) and Fig. 6(g) depict the refractive index distribution structures of the DBS-designed device and HPO-designed device, respectively. Figure 6(b) and Fig. 6(h) are the insertion loss curves of the 4 × 4 devices designed by DBS and HPO, respectively, versus the number of iterations. Similar to the previous two devices, the HPO method results in better device performance with fewer iterations. Figure 6(c–f) and Fig. 6(i–l) show the light field distribution diagrams of the DBS-device and HPO-device at 1550 nm, respectively, when the input channels are IN1, IN2, IN3 and IN4, respectively.
Fig. 6. Structure and performance of 4 × 4 devices designed by DBS and HPO. (a) Device structure optimized by DBS. (b) Insertion loss of the DBS device with respect to the number of iterations. (d)-(f) Light field distributions of the DBS-designed device. (g) Device structure optimized by HPO. (h) Insertion loss of the HPO device with respect to the number of iterations. (i)-(l) Light field distributions of the HPO-designed device.
Figure 7 shows the performance of the final structure designed by DBS and HPO. Figure 7(a–c) and Fig. 7(e–g) show the light fields of the two devices under light sources of 1530, 1545, and 1565 nm, respectively, when the input channel is IN1. It can be seen that the light intensity distribution in the white frame of the DBS device is slightly different under different wavelength light sources. In contrast, for our HPO device, in the 1530–1565nm band, the light fields are highly consistent. This indicates that the device designed by HPO still maintains a high degree of function stability even in the complex case of 4 × 4. Figure 7(d) and Fig. 7(h) show the insertion losses of this structure when the input channels are IN1, IN2, IN3 and IN4 and the output channels are OUT3, OUT4, OUT1 and OUT2, represented by T13, T24, T31 and T42, respectively. From the calculation, in the entire C-band, the four-channel insertion loss of the device designed by the DBS algorithm is up to -2.1dB, and the crosstalk is up to -23dB. Meanwhile, for the HPO device in the C-band, the highest four-channel insertion loss is -0.19dB, and the highest crosstalk is -22dB. Comparing the two crossed waveguide devices designed by the DBS algorithm and HPO, the HPO method reduces the insertion loss from -2.1dB (DBS-designed device) to -0.19dB (HPO-designed device), and the crosstalk is only slightly higher. Here, as the device becomes more complex and the optimization goal becomes more difficult, the performance of the device designed by DBS is seriously degraded, no longer meeting the design requirements.
Fig. 7. Light fields of different wavelengths and insertion lose curves of DBS- and HPO-designed devices. (a-c) Light field diagrams of the DBS device under 1530, 1545, and 1565nm light sources. (d) Insertion loss curve of the DBS device. (e-g) Light field diagrams of the HPO device under 1530, 1545, and 1565nm light sources. (h) Insertion loss curve of the HPO device.
To verify the scalability of our HPO method, we also designed an 8 × 8 UC-WC device. We tried to use the DBS method to optimize an 8 × 8 UC-WC device. However, because of the device complexity and too many optimization goals, DBS failed completely. More than half of the eight channels have an insertion loss of -10dB, and some channels even reach -30dB; hence, we have not included its results. Figure 8 shows the structure and performance diagram of the 8 × 8 device designed with HPO (size: 8µm × 8µm). Figure 8(a) shows the refractive index distribution structures of the HPO device. Figure 8(b) shows the insertion loss of the HPO device when the input channels are IN1, IN2, IN3, IN4, IN5, IN6, IN7 and IN8 and the corresponding output channels are OUT1, OUT3, OUT5, OUT7, OUT2, OUT4, OUT6 and OUT8, represented by T11, T23, T35, T47, T52, T64, T76 and T88, respectively. For the complex 8 × 8 device, the highest insertion loss among the eight channels in the entire C-band is only -0.2dB, and the crosstalk is lower than -28dB. For an extremely complex device with multiple optimization targets, such an ultralow insertion loss can still be achieved, which shows that our HPO has extremely good scalability and excellent optimization ability. It is worth mentioning that in the 8 × 8 structure, we set the original 5 × 5 pixels as a new pixel and change to 10 × 10 pixels as a new pixel, which takes into account the calculation time. These changes ensure that the required calculation time for one iteration is only 1/4 of the original, and the device performance is excellent. Figure 8(c) presents the curve of the insertion loss of the 8 × 8 device optimized by HPO with respect to the number of iterations. In Fig. 8(d–k), we illustrate the light field distribution diagrams of the device designed by HPO when the light source is 1550nm and the input ports are IN1, IN2, IN3, IN4, IN5, IN6, IN7 and IN8. It can be seen that the light follows the planned path.
Fig. 8. Structure and performance of the 8 × 8 device designed by HPO. (a) Device structure. (b) Insertion loss versus number of iterations (c) Insertion loss curve. (d)-(k) Light field distributions.
In the above-mentioned 2 × 2, 3 × 3, 4 × 4 and 8 × 8 UC-WC devices structure and performance analysis, we can clearly observe that, as the function of the DBS-designed devices becomes more complex, their performance rapidly degenerates or even fails completely. In contrast, the HPO method proposed herein has its unique advantages in designing ultra-compact, high-performance complex photonic devices. This is because it combines the adjoint method with the DBS algorithm, thus having the advantages of them both. The adjoint method can quickly find a structure with good performance based on the gradient in the continuous parameter space, and next the local optimization ability of DBS is employed to further improve the performance. We compare the UC-WC of our results with other reported waveguide crossings [5,7,11,28], and the comparison are shown in Table 1. It can be seen that the UC-WC with HPO design can further reduces the insertion loss, and still maintain good performance even for complex case of 8 × 8 UC-WC.
Table 1. Comparison of our UC-WC and reported waveguide crossings.
Various topology-optimized devices have been experimentally fabricated [12,13,41], with the help of advanced micro-nano fabrication technology. In Ref. [13], a two-channel focused wavelength demultiplexers was fabricated accurately with a footprint of 2.4µm × 10µm, on a SOI platform with 220 nm top silicon layer and 2µm buried oxide layer. These geometric patterns were exposed with electron-beam lithography (EBL), and precisely transferred to the top silicon layer with inductively coupled plasma (ICP) etcher. Comparing the insertion loss and crosstalk between experiment and simulation, experimental results is slightly worse. Here, taking 2 × 2 UC-WC as an example, we further analyze the fabrication tolerance [13,21]. We analyzed the cases of edge expansion (+) or contraction (-) of 2 nm, 4 nm, and case of random expansion or contraction of ±1 nm for each edge pixel. The transmission performance is given in Fig. 9, where random 1 case and random 2 case are two independent random error settings, respectively. As shown in Fig. 9, Interesting, the “+2nm” case retains little better performance than the “-2nm” case, and the “+4nm” case retains better performance than the “-4nm” case. A reasonable reason is that “-” etching errors lead to a little “thin” topography of device, causing some disappearance of originally small areas, which result some locally significant changes of propagating electromagnetic field. In contrast, “+” etching errors lead the topography being slightly “thick”, and the original area (whether large or small) will continue to be maintained, being conducive to maintaining the overall stability of propagating electromagnetic field. Basically, it is shown that the fabrication error does lead to certain degradation of device performance. Fortunately, recent reports show that the fabrication error can be well controlled and the insertion loss reaches the range of -0.5 dB [21,41]. The rapid improvement of nowadays manufacturing process give us the confidence to see UC-WC fabrication being consistent with the design in a near future.
4. Conclusion
In this paper, we propose an HPO design method that combines the adjoint method with the DBS. Using the proposed method, a series of ultra-low loss, ultra-compact multichannel waveguide crossing devices, including 2 × 2, 3 × 3, 4 × 4 and 8 × 8 devices, were designed. The obtained results are as follows. In the 1530–1565nm, the size of 2 × 2 device is 4µm × 3µm, the insertion loss is lower than -0.05dB, and the crosstalk is -34dB. The size of 3 × 3 device is also 4µm × 3µm, its highest insertion loss is -0.07dB, and the crosstalk is -33dB. The size of 4 × 4 device is 4µm × 4µm, the highest insertion loss is -0.19dB, and the crosstalk is -22dB. The size of 8 × 8 device is 8µm × 8µm, the highest insertion loss is -0.2dB, and the crosstalk is -28dB. We demonstrate that our HPO is highly scalable as a method for designing high-performance, ultra-compact photonic devices. The aforementioned results show that the proposed design method is feasible. In addition, the UC-WC device proposed herein has great potential for application in large-scale photonic integrated circuits in the future.
Funding
Program for New Century Excellent Talents in University (NCET-12-0142); Natural Science Foundation of Hunan Province (13JJ3001); Foundation of NUDT (JC13-02-13, ZK17-03-01); Innovation Support Program for Overseas Students in Chongqing (cx2021008); China Postdoctoral Science Foundation (2018M633704); Innovation Research 2035 Pilot Plan of Southwest University (SWU-XDPY22012); Science Fund for Distinguished Young Scholars of Chongqing (cstc2021jcyj-jqX0027); National Natural Science Foundation of China (60907003, 61805278, 61875168).
Disclosures
The authors declare no conflict of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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