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We demonstrated a 8×8 broadband optical switch on silicon for transverse-electrical polarization using a switch-and-selector architecture. The switch has a footprint of only 8 mm × 8 mm, minimum on-chip loss of about 4 dB, and a port-to-port insertion loss variation of only 0.8 dB near some spectral regions. The port-to-port isolation is above 30 dB over the entire 80-nm-wide spectral range or above 45 dB near the central 30 nm. We also demonstrated a switching power of less than 1.5 mW per element and a speed of 2 kHz, and estimated the upper bound of total power consumption to be less than 70 mW even without optimization of the default state of the individual switch elements.
© 2012 Optical Society of America
1. Introduction
Space-division optical switches which route signals among multiple sources and destinations are an essential part of flexible and intelligent optical communication systems [1]. Applications include network switching nodes and interconnections among servers, modules and even microprocessors. Many different switching technologies have been developed, most notably optical microelectromechanical systems (MEMS)-based switching and thermal optical switching on silica-based planar lightwave circuits (PLC). The optical MEMS technologies [2] allow very low crosstalk, small wavelength- or polarization-sensitivity, and scalability to large port counts, and are widely used in high-capacity optical crossconnects. However, they usually require large footprint, high driving voltage, and high power consumption. With PLC-based switches, switch matrix of 8×8 and 16×16 have been demonstrated with very good optical performances [3, 4]. However, both the device footprint (85 mm × 85 mm for the 8×8 switch) and the switching power (1.4 W) are still large [5]. Here we report 8×8 optical switch on silicon-based photonic integrated circuits (PICs), where the device footprint is more than 100 times smaller, and power consumption is more than 20 times lower than that of the silica-PLC switches. Although the switch currently works with transverse-electric (TE) polarization only, it can be easily adapted to polarization-independent operation with thicker silicon waveguides.
2. N×N switch architecture
Several architectures have been demonstrated for N×N optical switches. One example is the crossbar architecture with a N2 switch matrix [6, 7]. This is particularly suitable for optical MEMS technologies, where each switch cell could be a retractable mirror. Implementing this on planar waveguides is difficult for large port counts because of insertion loss of the switch elements. Here the number of switch elements within an optical path varies from 1 to 2*N-1, inducing large insertion loss as well as loss variations. An improved architecture, namely the path-independent insertion loss (PI-LOSS) arrangement, rearranges the switch matrix to have the same number (N) of elements for all optical paths and greatly improves the loss uniformity [8]. For both crossbar and PI-LOSS architectures, one might use two stages of Mach-Zehnder interferometers (MZI) within each switch element, for example a double-gate configuration, to improve the optical isolation. This increases the maximum MZI counts in the optical paths to 4*N-2 and 2*N, respectively. Although such linear scaling is manageable for N up to 16 for silica-based switches thanks to their extremely low-loss optical components, it becomes very difficult for high-index-contrast platforms such as silicon where the optical losses are significantly higher.
Here we use a switch-and-select architecture on silicon where the number of switches is uniform in all optical paths and follows logarithm scaling instead of the linear scaling. An example with N=8 is shown in Fig. 1, with thick blue lines showing examples of path configurations. The switch consists of an input switch array, an output switch array, and a passive crossover network. The input / output switch arrays are constructed from N copies of 1×N switch units, which are constructed from log2N stages of 1×2 switch cells. The passive crossover network connects the N2 outputs from the input switch array to the N2 inputs of the output switch array. To switch the i-th input to the j-th output, the 1×N input switch unit associated with the i-th input is configured to deliver light to its j-th output, and the 1×N output switch unit associated with the j-th output is configured to receive light from its i-th input. Since the output switch unit is complementary to the input switch unit, this inherently is a double-gate configuration with enhanced port isolation, and allows one-to-one mapping without collisions.
Table 1 list a comparison of the main characteristics of the crossbar, PI-LOSS, and the switch-and-select architectures, all assuming the double-gate configuration. The total number of MZI switches are similar in all three cases. While both PI-LOSS and switch-and-selector architectures ensure uniform number of switches in all optical paths, the first architecture follows linear scaling while the second follows logarithm scaling. Although the switch-and-select architecture requires many waveguide crossings if implemented on a single integrated photonic layer, but the loss of waveguide crossings usually is much lower than that of MZI switches, and can be further reduced with multiple vertically integrated photonic layers. Assuming a moderate loss of 0.25 dB per MZI on silicon, the insertion loss due to MZI alone drops from 4.0 dB to 1.5 dB for N=8, and from 8.0 dB to 2.0 dB for N=16. The superior scaling of the switch-and-select architecture makes it possible to construct low-loss 8×8, 16x16, or even higher port count switches on silicon, provided that the loss in the passive crossover network is sufficiently low.
Table 1. Comparison of cross-bar and proposed N×N switches
3. Design of a 8×8 switch on silicon
We designed and fabricated a 8×8 switch on silicon using the switch-and-selector architecture. Figure 2 shows photos of the fabricated chip. It has a footprint of 8 mm by 8 mm, and is fabricated on a 200-mm-diameter wafers with 220-nm-thick silicon using complementary metal-oxide-semiconductor (CMOS) compatible processes. Currently the switch is designed only for TE polarization because the small thickness of the silicon waveguides induces large birefringence and high crossing loss for the transverse-magnetic (TM) polarization. In the future it can be easily adapted to polarization-insensitive designs with thicker silicon waveguides as demonstrated very recently in Ref. [9].
Fig. 2 Photos of a fabricated 8×8 optical switch chip on silicon: (a) Entire switch chip. (b) An 1×8 switch unit. (c) An 1×2 switch cell. (d) Part of the passive crossover network. (e–f) Examples of waveguide joints with tight bends.
3.1. Input output switch array
The input and output switch arrays are built from independent 1×8 switch units, which in turn contain seven 1×2 switch cells that are arranged in three stages and tightly folded as shown in Fig. 2(b). The 1×2 switch cell, as shown in Fig. 2(c), uses a symmetric MZI with two thermooptical phase shifters and two adiabatic 50/50 power splitters. Such adiabatic splitters have a much broader bandwidth than conventional directional couplers and lower insertion loss than multimode interferometer splitters, which is critical especially for high-index-contrast waveguides. Shallowly-etched ridge waveguides are used to enhance mode interactions in the couplers. Around the phase shifters we etched trenches and partially removed the silicon substrate. This cuts down thermal leakage through the cladding and substrate, and reduces switching power as well as thermal crosstalk. The chip has 224 heaters, all of which are connected to two shared ground pads. The heaters use a thin layer of TiN, have a resistance of approximately 1 kΩ, and have a separation of approximately 50 μm between heaters from neighboring switch cells.
3.2. Passive connection network
The passive crossover network uses planar waveguide crossings and joints. Examples are shown in Figs. 2(d)–2(f). This solution is much more compact and robust compared to crossover networks using mirrors, but the insertion loss due to waveguide crossings can be a challenge. The maximum number of crossings in the optical path as well as the maximum variation among different paths scale as (N–1)2. For N=8 and a loss variation target of 1 dB, the insertion loss per crossing should be no more than 0.02 dB. In addition, the waveguide pitch in the network needs to be small to minimize the device footprint. For these reasons we use shallowly-etched, wide ridge waveguides for low-loss crossings, and fully-etched, narrow rib waveguides for waveguide joints. The waveguide pitch is 80 μm. In regions with limited spaces, s-bends (see Fig. 2(f)) are used to allow room for the waveguide joints.
Figure 3 show further details about the crossing and joint designs. Figure 3(a) is a schematic of the waveguide crossing. For visualization here we show only the silicon core without the surrounding silica cladding. In our experiment we choose W=6 μm. The corresponding fundamental TE mode profile is shown in Fig. 3(b). The large horizontal mode size (about ten times the wavelength in silicon) and shallow etch depth reduce the mode diffraction and scattering in the crossing region, and result in extremely low crossing losses. The calculated results with three-dimensional finite-difference time-domain methods are shown in Fig. 3(d), with a loss of around 0.015 dB at 1550 nm. In comparison, the crossing loss for a 500×220 nm fully-etched rib waveguide is 1.2 dB, which is nearly two orders of magnitude higher. The crosstalk of the shallow-etched ridge waveguide crossing is simulated to be below −40 dB. Before any waveguide joints, the shallowly-etched wide ridge waveguides are transitioned to fully-etched rib waveguides using exponential tapers (see Fig. 3(c)) to allow tight bends.
Fig. 3 Designs of waveguide crossings and joints. (a) Schematic of the waveguide crossing. (b) Fundamental TE mode of the ridge waveguide. (c) Schematic of the ridge-rib waveguide transition before joints. (d) Calculated crossing losses.
4. Characterizations of the 8×8 switch on silicon
The fabricated chip is characterized without any optical / electrical packaging. As a result, port-to-port responses are characterized sequentially by moving input and output fibers and probe cards with multiple DC needles. All fiber positioning and heater powers are manually adjusted, and thus might not reach their optimum settings. Due to the difficulty in testing the un-packaged device, only characteristic port-to-port responses are measured instead of all 64 configurations.
4.1. Insertion loss
The fiber-to-fiber insertion loss is first measured from port I1 to port O1, which has the longest path length and no waveguide crossings. As shown in Fig. 4(a), the measured total insertion loss is 11.8 dB at 1500 nm and 10.5 dB at 1580 nm, with a variation of 1.3 dB over a 80-nm-wide wavelength range. We estimate the coupling loss between the cleaved single-mode fibers and the silicon waveguides to be roughly 3.5 dB/facet with the assistance of a silicon inverse taper and a 6 μm x 6 μm SiO2 cantilever [10]. Further coupling loss reduction can be achieved by replacing the air-cladding of the cantilever with index-matched oil or epoxy to improve the mode matching. The on-chip loss is thus estimated to be ∼4.0 dB. This includes six 1×2 switch cells, four ridge-rib waveguide transitions, and 1.6-cm-long waveguides, most of which are wide shallow-ridge waveguides with low propagation loss. The loss breakdown is listed in Fig. 4(b).
To characterize the insertion loss uniformity among different port configurations, we plot the transmission spectra from port I1 to all eight output ports in Fig. 5(a). Here the number of waveguide crossings increases from 0 to 49, which represents the best-case scenario (I1–O1) and the worst-case scenario (I1–O8) of the 8×8 switch. Relatively flat responses are observed for all eight cases. Near certain spectral regions (e.g., 1515 nm and 1580 nm), the insertion loss variation among all eight cases is only about 0.8 dB or less, which is consistent with the simulated loss of 0.015 dB/crossing. Near some other spectral regions (e.g., 1500 nm and 1565 nm), however, much larger variations of up to 2.8 dB are observed. Similar behavior is measured when the input port is switched to I2. The cause for such wavelength dependence is still under investigation, and one suspect is weak optical reflections at waveguide crossing interfaces. Note that the I1–O1 spectrum is slightly different than that in Fig. 4(a) since slightly different heater power settings were used during the two measurements.
4.2. Port isolation
Because of the complementary input / output switch arrays, the worst port-to-port isolation is expected to be twice the extinction ratio of a single 1×2 switch cell. To characterize this, we still use the example of transmission from I1 to O1. The ON-ON curve (blue) in Fig. 5(b) (same as Fig. 4(a)) is when all switches in the optical path are properly adjusted to allow maximum transmission, i.e., both input and output switches are configured to the ON state. Next, the last 1×2 switch cell in the input switch is set to the OFF state (which now delivers the optical power to port O2 instead), corresponding to the OFF-ON curve (red). From this one can measure the extinction ratio of the 1×2 switch cell to be above 16 dB over the the entire 80 nm wavelength, and up to a maximum of over 30 dB. Finally, we set the last 1×2 switch cell in the output switch also to the OFF state (which now accepts optical power from port I2 instead), corresponding to the OFF-OFF curve (green). The difference between the ON-ON curve and the OFF-OFF curve is the port-to-port isolation. One can clearly see that the double-gate configuration greatly enhances the isolation to above 30 dB over the entire spectrum and above 45 dB near the central 30 nm. Similar responses are observed for other port configurations that we have measured.
4.3. Switching power and speed
We also measured the switching power of each 1×2 switch cell and estimated the maximum total power consumption of the 8×8 switch chip. Figure 6(a) shows the optical transmission from I2 to O1 for a wavelength of 1540 nm while the heater power of one 1×2 switch within the optical path is adjusted. One can see that the heater power required for a π-phase shift is less than 1.5 mW, with an extinction ratio of close to 20 dB. This switching power is more than 25 times lower than the best switches on silica waveguides, and is attributed to strong thermooptical effect of silicon (which is 10 times stronger than that of silica) and the good thermal leakage suppression with the isolation trenches and substrate removal. For the entire 8×8 switch chip, the maximum number of switches that require tuning for any given switching configuration is 48 (eight optical paths × six switch cells per path). Therefore the maximum total power consumption is only 70 mW. Note that this is the absolute upper bound, and the power can be significantly reduced if the default state of the switch cells (when no thermal tuning is applied) can be properly designed. For example, if the default state of a switch cell is either the ON or OFF state, then it only requires tuning power for half of all switching configurations, effectively cutting the power consumption by a factor of two.
Fig. 6 Characterization of 1×2 switch cells: (a) Normalized optical transmission as a function of heater power at 1540 nm. (b) Temporal response of transmission during switch.
The switching speed is characterized with a rectangular electrical signal applied to the heater. The normalized temporal transmission is shown in Fig. 6(b) with a signal frequency of 200 Hz. We measured a 20%–80% rise and fall time of close to 250 μs, indicating a maximum switching speed of close to 2 kHz. This is slower than typical thermal switches on silicon as a result of suppressed thermal diffusion, but is still comparable or faster than silica-based thermal switches or MEMS devices. For port reconfigurations that happen rather infrequently, this switching speed is sufficient.
4.4. Thermal crosstalk
When so many thermal switches are so densely packed on a small chip, thermal crosstalk between neighboring switch units could be a major concern. To characterize this, we monitored the optical transmission change for a certain optical path, while the heater power of a neighboring switch unit outside of the measured optical path is adjusted. The results are shown in Fig. 7. One can see that increasing heater power does induce transmission change as a result of thermal crosstalk. For 8 mW of heater power applied, the transmission changes by up to 0.35 dB. When the heater power is 1.5 mW, which corresponds to a π-phase change in the neighboring switch, the transmission change is only 0.1 dB, corresponding to phase change of 0.1π. Further improvement in thermal crosstalk can be achieved with slightly larger heater separations and/or reduced thermal crosstalk through shared ground metals.
Fig. 7 Change in optical transmission when a neighboring heater outside of the optical path is adjusted.
5. Conclusion
We demonstrated a compact, low-loss and low-power 8×8 broadband optical switch on silicon using a switch-and-selector architecture. The switch uses an array of 1×8 switch units at the input side and the output side, and an 64×64 passive crossover network between the switch arrays. It allows uniform number of switch cells in any optical paths and follows logarithm scaling with the port count N, which is critical for implementation on high-index-contrast PIC where the optical component losses are significantly higher than silica-based PLC. Thanks to the large index contrast, we built the device with a footprint of only 8 mm × 8 mm, which is about 100 times smaller than similar switches on silica. The minimum on-chip loss is about 4 dB, with a port-to-port insertion loss variation of only 0.8 dB near some spectral regions. The loss variation increases to up to 2.8 dB near some other spectral regions and the cause is still under investigation. The port-to-port isolation is above 30 dB over the entire 80-nm-wide spectral range and is above 45 dB near the central 30 nm. We also demonstrate very low switching power of less than 1.5 mW per π phase shift, and estimated the upper bound of total power consumption of the entire switch to be less than 70 mW even without optimization of the default state of the individual switch cells.
Further improvements that are required before practical applications of such switches include: 1) polarization-independence and temperature-independence of the switch elements, 2) improvement of the crossover network for reduced insertion loss variations, and 3) improved fiber coupling. The first issue on polarization-independence and temperature-independence can be solved with thicker silicon waveguides with minimized birefringence, and a properly-designed current source as the heating control, which have been recently demonstrated for a 1×8 switch on silicon [9]. The second issue on the crossover network can be solved with better crossing designs with reduced crossing loss. For even larger port count, three-dimensionally integrated PIC with two vertical layers of waveguides can be envisioned to eliminate crossing losses. The fiber coupling loss can be improved with better spot-size-converter with matched cladding index to about 1.5 dB/facet. With these improvements, we believe such compact, low-loss and low-power silicon switch will find many applications in network switching nodes and optical interconnections.
Acknowledgments
We thank Tsung-Yang Liow and Guo-Qiang Lo from the IME for fabrication, Christopher R. Doerr for helpful discussion, David Neilson and Martin Zirngibl for support, and Jeanette Fernandes for assistance.
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