1. Introduction

For the last decade, optical packet switching (OPS) has been intensely investigated as one of the key technologies for coping with the explosive growth of Internet-related traffic in optical communication networks, enabling next generation photonic networks. OPS has the potential to maximize bandwidth utilization, network scalability, and traffic engineering capability as a result of packet-level data granularity while resolving the power consumption issues faced by today’s electrical routers/switches [1–3]. However, realization of the OPS router necessitates forwarding functions of label processing, switching, and buffering be achieved for high-speed asynchronous variable-length optical packets on a per packet basis. For implementing the label processing and buffering functions, all-electrical approaches have difficulty handling high-speed asynchronous packets without a preamble for clock recovery, and consume large amounts of power [2]. On the other hand, for the switching function, all-optical approaches show promise, but face extreme challenges in implementing complex label/packet processing functions [2], and offer only discrete-time buffering based on fiber delay lines [4].

To overcome these shortcomings, we have proposed a hybrid optoelectronic router, combining both optical and electrical technologies to create an OPS node that reduces power and latency while maintaining functionality [2]. As an example, the router employs a hybrid optoelectronic buffer in which optical/optoelectronic interface devices are combined with complementary metal–oxide–semiconductor (CMOS)-based electronic memory. The low-power devices allow the interfacing of high-speed, asynchronous, arbitrary-length optical packets without a preamble to the slower CMOS technology. CMOS memory then enables large capacity, arbitrary-time buffering as well as flexible, high-level processing functions for the optical packets in order to execute contention resolution and also support various network services (multicast, Quality of Service (QoS), etc.). In this letter, we describe a prototype hybrid optoelectronic buffer subsystem consisting of modules developed for the interfaces and a memory board integrating a field programmable gate array (FPGA) and other necessary components. Using this prototype, we demonstrate an optoelectronic buffer that can freely receive and generate 10-Gbit/s asynchronous variable-length optical packets, with error-free operation achieved for both functions.

2. Hybrid optoelectronic buffer for OPS router

Figure 1 shows our proposed OPS router architecture that incorporates the hybrid optoelectronic buffer shared between multiple transmission (space/wavelength) channels [2]. In the router, the packet data is organized into wavelength layers (four vertically overlayed planes in figure), separated and combined with arrayed waveguide gratings (AWGs). Incoming asynchronous arbitrary-length optical packets are first fed into label processors [5] located at every input port. In the label processor, each packet’s label is optoelectronically processed while the payload is maintained in the optical domain. Most packets are then passed to the desired outgoing port through the optical switch fabric (red line, Fig. 1), unless contention occurs, where two incoming packets request the same output port simultaneously. When contention occurs, the packet arriving later is forwarded through the switch to the shared optoelectronic buffer (blue line) which has input/output interfaces for each wavelength layer and a shared electronic (CMOS) buffer at the core. At the input interface, an all-optical serial-to-parallel converter (SPC) [6] converts the input high-speed optical packets into slow parallel signals when triggered by optical pulses generated from an optical clock pulse-train generator (OCPTG) [7]. The lowered bit rate of the parallelized signals enables writing the packet data to CMOS memory, where it is buffered for an arbitrary period until the desired output port becomes available. Once inside the electronics, various functions such as QoS differentiation, packet duplication and label processing for multicast routing, as well as switching between wavelength layers (to a less congested wavelength) can be performed on the packets because of CMOS functionality. In addition, 3R regeneration as well as forward error correction (FEC) of the packet signal can be implemented by forwarding packets to the buffer when they become degraded as a result of passing through the network [2]. The output interface of the buffer includes an electrical-to-optical parallel-to-serial converter (E/O PSC) [5] and another OCPTG. When triggered by the OCPTG, the PSC reconstructs the original optical packet from slow parallel electrical signals from the CMOS memory and sends it to the switch fabric.

 

Fig. 1 Diagram of proposed OPS router. AWG: arrayed waveguide grating. SPC: serial-to-parallel converter. PSC: parallel-to-serial converter. OCPTG: optical clock pulse-train generator.

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The router architecture incorporating the shared buffer performs buffering/processing of the entire packet only in specified instances, when there is the need to resolve contention or implement various services. This selective buffering scheme reduces the total required buffering capacity of the router, and hence power and size, and increases transparency of the router for reduced latency. The hybrid optoelectronic buffer thus enables a low-power, low-latency OPS router for high-speed asynchronous optical packets, capable of contention resolution, signal restoration, and supporting various network services.

3. Optical and optoelectronic interface devices

Figure 2 shows the OCPTG that generates optical clock pulses from asynchronous arbitrary-length optical packets without a preamble [7]. The OCPTG consists of an optical clock-pulse generator (OCG) and an optical pulse-train generator (PTG). The OCG generates a synchronized single optical pulse and a packet envelope electrical signal per incoming optical packet and the PTG multiplies the optical pulse. The OCG uses a sample-and-hold circuit fabricated as an InP-based optoelectronic integrated circuit (OEIC), consisting of metal-semiconductor-metal photodetectors (MSM PDs) and high-electron-mobility transistors (HEMTs). The OEIC generates an electrical step signal from the leading ‘1’ bit of the input optical packet. The rising edge of the step signal then triggers a pulse generating circuit, whose output gain-switches a laser diode to generate the optical pulse [2,7]. The fiber-loop based PTG is activated by the packet envelope signal to convert the optical pulse to an optical clock-pulse train with precise repetition rate (at the line rate divided by number of SPC/PSC channels) and duration matching the input packet length. Due to optical/electrical/optical (O/E/O) conversion within the OCG, the energy and polarization of the output optical pulses from the OCPTG are fixed, regardless of the input optical packet’s energy and polarization, a critical requirement for application to the SPC. For this study, a module integrating four OCGs on a 100x120mm² printed circuit board (PCB) and 580x104x25mm³ PTG modules were fabricated.

 

Fig. 2 Diagram of optical clock pulse-train generator (OCPTG) and photograph of pulse-train generator (PTG) module. OCG: optical clock-pulse generator. LN: Lithium Niobate. PC: polarization controller. PBS: polarizing beam splitter. SOA: semiconductor optical amplifier. PD: photodiode. EDFA: erbium doped fiber amplifier.

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Figure 3 shows a 1:16 all-optical SPC that employs an InP-based semiconductor surface-normal all-optical switch operating with a differential spin-excitation method [6]. Incoming optical packets are split into 16 copies, passed through delay lines with delay values staggered by the bit separation, enter a surface emitting planar lightwave circuit (PLC), and are output from the PLC surface in a hexagonal array by integrated 45° mirrors. Subsequently, the packets are converged on the all-optical switch, where two circularly-polarized pump pulses created from an output optical pulse of the OCPTG also irradiate the same spot on the switch. Timing of the pump pulses are set to coincide with the edges of the time window that encloses all 16 input bits (per clock pulse) for opening and closing the optical switch. As a result, only the bits within the time window are output from the switch as 16 parallel optical signals, and repetitive triggering by the OCPTG enables demultiplexing of variable-length optical packets. 1:16 SPCs have been demonstrated for 10-Gbit/s, 40-Gbit/s, 100-Gbit/s, and 1-Tbit/s optical packets [6,7]. For this study, 70x20x20mm³ SPC modules were fabricated.

 

Fig. 3 Diagram and photograph of all-optical serial-to-parallel converter (SPC). PBS: polarizing beam splitter. PLC: planar lightwave circuit.

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Figure 4 shows a 16:1 E/O PSC that constructs optical packets from stored data in the CMOS memory. The E/O PSC consists of an InP-based OEIC and an E/O converter [5]. The OEIC contains 16 optically triggered electrical switches (green squares in figure), using MSM PDs and HEMTs, placed along a transmission line. The input data entered into the 16 switches as slow parallel electrical signals are serialized onto the transmission line when the MSM PDs are triggered in turn with optical pulses, as the switches perform fast gating. For the PSC, a discharge-based configuration for the MSM drastically reduces the long fall time (due to slow holes) of the ordinary MSM PD (to ~3 ps for 50-ohm load), enabling ultrafast operation [5]. In practice, circuit parameters (capacitances and resistances) are chosen so that the PD output pulse has an appropriate sum of rise and fall times (~100 ps for 10-Gbit/s multiplexing operation). Finally, E/O conversion of the serialized signal creates the output optical packet. PSC modules were fabricated for this study by integrating the OEIC and driver circuits for the parallel input data onto a 80x58mm² PCB.

 

Fig. 4 Diagram of electrical-to-optical parallel-to-serial converter (E/O PSC) and photograph of PSC module. EA-DFB: electro-absorption modulator integrated distributed feedback laser. MSM-PD: metal-semiconductor-metal photodetector.

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4. Experiments

Figure 5 shows the CMOS memory board (300x365mm²), which has four inputs and outputs. The board contains an FPGA at the center, a 16-channel avalanche photodiode and transimpedance amplifier (APD-TIA) array at each input port for O/E conversion of the SP converted signals, a PSC module at each output port, an optical receiver circuit at each input/output port for receiving optical clock signals from the OCPTGs, and other necessary components such as power supply circuits. Two of the four input/output ports were functional at this time, equipped with the APD-TIA arrays and the PSC modules, as seen in the figure. Within the FPGA, 96-kbytes of buffering capacity was available for each input/output port pair, with a two-line queuing structure at the output for the QoS application. The memory board was combined with the SPCs and OCPTGs to create the prototype buffer subsystem.

 

Fig. 5 Photograph of CMOS memory board with four inputs and outputs. PSC: parallel-to-serial converter. APD-TIA: avalanche photodiode and transimpedance amplifier.

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To verify the operation of the prototype, bit error rate (BER) characteristics were measured for reception and transmission of 10-Gbit/s asynchronous variable-length optical packets. For write-in operation, an optical packet stream at 1552.5 nm having a non-return-to-zero (NRZ) format with various packet lengths (100-300 ns) and a 2⁷-1 pseudo-random binary sequence (PRBS) payload pattern was created by using a pulse pattern generator (PPG) (Fig. 6(a) ). Data occupied ~25% of the stream, with the remainder being the guard time between packets. The input packet stream was fed into the buffer through an O/E/O stage consisting of a burst-mode (DC-coupled), 10-Gbit/s APD-TIA, a modulator driver amplifier, and an electro-absorption modulator integrated distributed feedback laser (EA-DFB) which is driven by the APD-TIA output electrical signal. Note that the O/E/O stage was placed before the buffer in order to emulate the operation of the proposed OPS router (the optical switch in the router uses the O/E/O stage for forwarding packets to the buffer) [8]. After passing through the O/E/O stage, the input optical packet stream was then split in two: one fed to the SPC as data and the other fed to the OCPTG for clock generation. An optical clock-pulse train at 625-MHz repetition rate having ~1-pJ energy/pulse, ~10-ps pulse width, and duration matching the corresponding input packet was then generated from the OCPTG. The generated clock-pulse train was subsequently amplified to ~30 pJ/pulse and fed into the all-optical SPC as control pulses. With the control pulses, the SPC converted the 10-Gbit/s packet data to 625-Mbit/s, 16-parallel optical signals. Width of the gating time window for the SPC was set to ~50ps, corresponding to about half the bit period of the 10-Gbit/s data. The parallelized signals were converted to electrical signals by the slow (~400MHz bandwidth) 16-ch APD-TIA array and then stored in the memory in the FPGA. For this write-in operation at the FPGA, the optical clock pulses from the OCPTG were also used as a latching signal for the 16 parallel data. For the write-in BER testing, received power was defined as the power fed to the O/E/O stage placed before the buffer, and error rate was measured by comparing the stored data with the reference PRBS data in the FPGA. Next, for read-out operation, the FPGA began the operation by generating an electrical packet envelope signal, based on the output packet length value which is stored in the CMOS. From the envelope signal, another OCPTG then generated an optical clock-pulse train with duration matching the corresponding length of the output packet. (Note that the OCG of the read-out OCPTG uses a packet envelope signal from the CMOS as the step signal required for generating a single optical pulse. Thus, the OEIC for generating the step signal is omitted in the read-out OCG.) Triggering the FPGA with the clock pulses from the OCPTG causes the 16-parallel data to be fed into the PSC. The PSC, which is also triggered by the clock pulses from the OCPTG, interleaves the data to create a 10-Gbit/s optical packet stream. Error rate for the read-out operation was measured with a conventional error detector (ED), preceded by the same burst-mode 10-Gbit/s APD-TIA and amplifier used for the write-in operation. In order to use the conventional ED (not burst mode compliant), the ED and the memory board were synchronized with each other. As shown in Fig. 6(b), error-free operation was obtained for both write-in and read-out operations with a sensitivity of −23.3 dBm and −20.5 dBm, respectively (limited by the modulator driver amplifier sensitivity). The power penalty for the read-out is due to the slightly degraded quality of the signal from the E/O PSC compared to the write-in signal created directly from the PPG. The degradation is likely caused by variation of electrical switch response time (fall time) in the PSC due to optical clock power fluctuation.

 

Fig. 6 (a) Waveform of 10-Gbit/s packet stream used for BER measurements. (b) Results of BER measurements for buffer write-in and read-out operation.

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To demonstrate compactness of the fully assembled system, the system was housed in three 19-inch-rack-mountable shelves (43x76x8.5cm³), one each for the input optical clock generators (4ch), the output optical clock generators (4ch), and the remaining components including the memory board, SPCs, and PSCs. All other necessary components, such as EDFAs, thermo-electric cooler drivers, optical filters, and power supplies, were included in the three shelves. A single 24-V power supply connection on each back panel provides power.

5. Conclusion

We have constructed a prototype hybrid optoelectronic buffer that combines all-optical and optoelectronic interface devices with CMOS-based electronic memory. The burst-mode compliant low-power interfaces allow write-in/read-out of high-speed asynchronous arbitrary-length optical packets to/from CMOS. The CMOS-based buffer provides any desired function, such as QoS differentiation and packet duplication for multicast routing as well as arbitrary time buffering, 3R regeneration, and wavelength conversion. With the prototype buffer subsystem, error-free write-in and read-out operation of 10-Gbit/s asynchronous variable-length optical packets has been demonstrated. The optoelectronic buffer is essential for realization of a low-power, low-latency OPS router that forwards high-speed asynchronous optical packets and supports various network services.