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We present an experimental demonstration of simultaneous chromatic dispersion and self-phase modulation compensation at 10.7 Gb/s using real-time electronic digital signal processing. This was achieved using a pre-distorting transmitter based on commercially available field programmable gate arrays and 21.4 GS/s, 6-bit resolution digital-to-analog converters. The digital signal processing employed look-up tables stored in RAM. This resulted in the achievement of a BER of 10−6 at an OSNR of 16 dB after transmission over a 450 km link of uncompensated standard single mode fiber with + 4dBm launch power.
©2009 Optical Society of America
1. Introduction
There has been considerable recent interest in electronic compensation using electronic digital signal processing (DSP) [1]. Application specific integrated circuit (ASIC) implementations have been demonstrated which compensate for large quantities of chromatic dispersion using the transmitter-based electronic predistortion (EPD) technique at 10 Gb/s [2] and the receiver-based digital coherent approach at 40 Gb/s [3]. Implementations based on field programmable gate arrays (FPGAs) have also been shown to be capable of >1000 km linear transmission at 10 Gb/s [4]. Real time compensation of polarization mode dispersion (PMD) has also been proved at 10 Gb/s and above using maximum likelihood sequence estimation (MLSE) [5] and the digital coherent receiver [3].
There is also considerable interest in the compensation of nonlinearities such as self-phase modulation (SPM). Experiments with off-line processing have been presented using electronic predistortion [6] and coherent detection with postcompensation in [7,8]. Nonlinear filters based on look-up tables (LUTs) stored in random access memory can be used to compensate for SPM as described in [9,10]. An alternative approach is to solve the non-linear Schrödinger equation in real time [11]. However, few detailed descriptions of the practical implementation of DSP for SPM compensation have been published for either transmitter or receiver-based techniques.
In the work presented in this paper, the precompensating transmitter, based on a Cartesian Mach Zehnder modulator, shown in Fig. 1 , generates predistorted signals in such a way that the fiber dispersion and nonlinearity reverse the distortion during transmission, resulting in the desired signal waveform at the receiver.
Nonlinear filters are used to generate the modulator drive waveforms. The filter implementation used in this work makes use of look-up tables stored in RAM. A schematic of the method is shown in Fig. 2 [9]. The incoming bit sequence is stored in a register, and to set each output sample, n consecutive bits address the look-up table which outputs an m bit word to the D/A converter. The sample rate of the D/A converter is set to twice the bit rate.
The entries in the LUT are calculated by split-step Fourier method simulations of the back-propagation [12] of the signal through the link. Using a pseudo random binary sequence (PRBS) allows the LUT entries corresponding to each n bit word to be obtained and subsequently programmed into the FPGA.
The paper presents results showing the simultaneous compensation of chromatic dispersion and SPM using real time processing implemented on FPGAs in transmission over links of up to 700 km of uncompensated standard single mode fiber. The 10.7 Gb/s predistorting transmitter is based on the design described in [4], with the exception that commercially available digital-to-analog converters (DACs) with 6-bit resolution were used and LUT-based digital filters were used to enable SPM compensation to be performed. The transmitter and other experimental details are described in detail in Section 2. The DAC used in this work allowed partly automated synchronization of the FPGA outputs rather than the manual technique used in [4]. The synchronization scheme is described in Section 3. The results for both linear and nonlinear (NL) transmission, including the sensitivity to non-optimal control settings for the modulator are presented in Section 4. The results are discussed and conclusions drawn in Section 5.
2. Transmission setup
The optical link considered in this work is shown in Fig. 3 , representing a typical link in which some design decisions are made based on practical achievability and not to optimize transmission quality.
Fig. 3 Schematic representation of the setup (Gray blocks are used for synchronization processes). DS – dual stage, SS – single stage, t – oscilloscope, f – spectrum analyzer.
Field programmable gate arrays (FPGAs) were used to implement the DSP because of their lower cost and the faster development times compared to the development and implementation path for an ASIC.
The DSP was implemented at the transmitter to predistort the signals. Predistortion has a number of advantages compared to receiver-based equalization. These include, firstly, the current availability of commercial high speed (25 GS/s) digital-to-analog converters with time multiplexers (DAC/MUX), while analog-to-digital converters (ADC), required for receiver-based DSP are yet to become generally available [13,14]. Secondly, the constant availability of a suitable clock for the DSP circuits at the transmitter without requiring clock recovery makes the scheme simpler to implement than receiver-based signal processing. Thirdly the optical set-up, based on a Cartesian Mach-Zehnder modulator at the transmitter for amplitude and phase modulation and a direct-detection receiver is simpler than the coherent receiver required to achieve effective chromatic dispersion compensation.
The port count and speed of available FPGA-DAC/MUX resulted in sample rates of up to 25 GS/s. As two samples per bit are required for high quality compensation, the standard bit rate of 10.7 Gb/s (10 Gb/s payload plus 7% FEC overhead) was chosen.
The setup has many similarities to the one described in [4] with the major differences being:
The FPGAs used were Xilinx Virtex 4 type XC4VFX140 instead of the FX100. The additional IO ports made it possible to use D/A converters with 6 bit resolution (rather than the 4 bit resolution used in [4]).
The DAC/MUX was not constructed from discrete components, but a commercially available integrated circuit (IC) incorporating digital to analog conversion, time multiplexing and other functionalities was used [14] This made it possible to automate part of the synchronization process.
A straight line link was used, rather than a circulating loop, allowing continuous transmission.
Predistortion was implemented with LUT based filters, rather than finite impulse response (FIR) filters, making it possible to predistort for nonlinear as well as linear effects (i.e. self phase modulation (SPM) in addition to chromatic dispersion (CD)).
2.1 Transmitter design
The transmitter (Fig. 3) uses a LiNbO3 based Cartesian Mach-Zehnder (MZ) modulator. This type of modulator is also referred to as an I-Q modulator, triple MZ modulator or DQPSK modulator. It is based on two MZ modulators, the optical signal passing through one of the two Mach Zehnders is delayed by π/2 so that one MZ delivers the inphase (I) component and the second MZ the quadrature (Q) component of the optical signal, allowing control of the phase and amplitude of the optical transmitted signal. In our setup each of two drive signals was generated by identical components (FPGA + DAC/MUX), the only difference being the code loaded into the FPGA and the settings of the control voltages.
A block diagram of the FPGA code and interaction with the DAC/MUX is shown in Fig. 3, where it can be seen how the analog signal driving one of the two arms of the Cartesian Mach Zehnder is produced. The signal for the second arm is constructed by a similar design but with a different predistortion table applied to the signal in the LUT block. In Figs. 3 and 4 the gray blocks are related to the synchronization processes described in the next Section.
Fig. 4 Block diagram of the internal working of FPGA in combination with DAC for a single arm. Gray blocks are used for synchronization processes. Block A represents 63x the LUT block for the parallel processed bits of the pattern, blocks B, C, D, E represent parallel processed data for the 23 other IO ports.
A test sequence containing a PRBS of 213 was stored in a memory on the FPGA. This memory was driven by an address counter. To achieve a bitrate of 10.7 Gbit/s with the internal logic of the FPGA being clocked at 167.33 MHz, it was necessary to process 64 bits in parallel.
The compensating filters were based on lookup tables (LUTs), using the method described in [7]. A predistorted waveform (amplitude and phase) was calculated off-line for the central bit-period of each possible 11 bit sequence using an inverted (negative nonlinearity, attenuation and dispersion) split-step Fourier method and divided into I and Q component. The optical model included dispersion and non-linear effects, following the method published in [15]. The nonlinear characteristics of the modulator were also included in the calculation of the LUT entries. Sorting and quantizing the calculated predistorted signal resulted in a LUT of 211 entries and a word size of 12 bit (2 samples with 6 bit resolution). A larger LUT enables greater chromatic dispersion and nonlinearity to be compensated. However, the size of the LUT scales exponentially with transmission distance [7] and in this case is limited by the amount of block RAM available on the FPGA.
A sequence of 11 bits in time of the test sequence was used as the address for the LUT table. We stored multiple LUTs on the FPGAs to be able to switch between different link scenarios without requiring reprogramming of the FPGAs. The number of LUTs that could be implemented depended on the efficiency of the synthesis engine used. We were able to design systems containing from two to four 11 bit LUT tables into the FPGA. Attempting to add more LUT tables resulted in the synthesis engine starting to use general logic gates instead of block memory for the LUTs, complicating the process of achieving timing closure for the design. The resources used for multiple LUTs could instead be used to achieve a single larger LUT and hence the compensation of larger amounts of distortion. In this case the design could be modified to allow the LUT entries to be updated from an external slower memory.
The LUT outputs give 12 bits describing the shape of the modulator drive voltage waveform over a single bit period, in the form of two samples with 6 bit resolution. With 64 LUTs in parallel, this resulted in a 768 bit (64x12 bit) databus. This databus was reordered by the Reorder block (Fig. 4) to ensure the correct 24x32 bit signals were transferred to each IO port, to be send to the DAC/MUX [14].The peak-to-peak (PkPk) level and DC offset of the modulator drive signals were adjusted to suit the modulation characteristics of the Mach-Zehnder modulator used, and the parameters used to calculate the LUT. To obtain maximal resolution, different PkPk settings were used for each LUT table.
2.2 Transmission link
The transmission link was constructed using commercial amplifier modules from an Ericsson long haul transmission product with integrated control algorithms and using fiber spools as transmission medium. The fiber was standard non-dispersion shifted fiber (NDSF) with estimated chromatic dispersion (D) of 17.2 ps/(nm km), a dispersion slope (S) of 0.0572 ps/(nm2 km) at reference frequency 193.1 THz and a nonlinear coefficient (γ) of 1.36 (W km)−1. The chromatic dispersion compensating fibers, normally present at the mid-stage of the dual-stage (DS) amplifiers were removed and replaced by attenuators.
At the mid-stage of the last dual stage amplifier, amplified spontaneous emission (ASE) white noise was added to enable the optical signal to noise ratio (OSNR) at the receiver to be controlled. The other 36 channels of the DWDM signal were filled with non-modulated signals following a 100GHz channel plan, but spaced by 200GHz from the electronic predistorted (EPD) channel to improve the accuracy of the OSNR measurement.
2.3 Receiver design
We measured the OSNR with an optical spectrum analyzer (OSA) measuring signal power over a 0.6 nm bandwidth and the noise at 0.4 nm away from the central frequency and normalised to power over 0.1 nm. The required channel was selected with a tuneable filter set to a bandwidth of 0.4 nm and input to a commercial receiver with clock recovery supporting a bitrate of 10.709 Gb/s and a sensitivity of −19.5 dBm for a BER of 10−12 at this bitrate. Its analog output and recovered clock signal were passed to a bit error rate analyzer in which the decision threshold and sampling point were manually optimized.
3. Synchronization
Synchronization consisted of two steps. First the 24 signals between FPGA and DAC/MUX were automatically synchronized (port synchronization). Then the two arms driving the Mach Zehnder were synchronized (arm synchronization).
3.1 Port Synchronization
The 24 signals from the FPGA to the DAC required to be synchronized within the DAC/MUX in which they are multiplexed and converted to the output analog signal. The 24x32 bit signals arriving internally at the IO ports of the FPGA are synchronized. The different IO ports of the FPGA have however different delays which can change when resetting the ports. This issue has been reported and a solution described in [16]. We used however a different method to solve this problem, which is described below. In our setup, the interconnections from FPGA to the DAC/MUX are also not phase matched and are a second source for misalignment.
We first carried out multiple measurements of the delays of the different ports of each FPGA while resetting them and calculated the average delay for each port. The average delay was hardcoded into the Fixed Port Delay block (Fig. 4.).
Because the delay could change when restarting or resetting the FPGA and/or DAC/MUX we also needed dynamic adjustment. This was implemented in the Variable Port Delay block. A Variable Port Delay block with an adjustable delay of up to 8 (23) bits was sufficient to achieve bit synchronization of all IO ports.
The digital nature of the FPGA implies that we cannot adjust the delay of the datastreams in the FPGA to the IO ports on a scale shorter than 1 bit period. Hence, we used the feature of the DAC/MUX to select the sampling point to obtain synchronization better than 1 bit period.
A port alignment algorithm in the FPGA communicated with the DAC/MUX. The port alignment algorithm first transmits a particular test sequence from the Test Sequences block to the DAC/MUX for 1.3 ms, and then interrogates the DAC/MUX to determine if alignment is achieved. If not, it adjusts the delay in the FPGA and sampling point in the DAC/MUX and repeats this until alignment is reached. Hardcoding the expected delay for each IO port also speeds up this process because fewer possible delays have to be checked. It took less than a second to achieve port synchronization in full automatic mode of all 24 ports.
3.2 Arm Synchronization
Synchronization between the two arms driving the in-phase and quadrature inputs of the Mach-Zehnder modulator is required to be considerably better than the duration of 1 sample period (47 ps). Arm synchronization comprises three steps.
The first step is automated. It consists of a start pulse exchanged between the two boards synchronizing the start of the address counters in the two FPGAs. Because the DSP logic in the FPGA is clocked at 167.33 MHz and the IO ports used to exchange the synchronization pulse signal were low speed ports, this method could only achieve an accuracy of 5980 ps. The result of this is manually checked by comparing the pattern trigger pulse (see Fig. 3.) and if necessary a manual correction of the memory address counter or a new exchange of a sync pulse is applied.
The second step is manual. We use one of the differential output port pairs of the DAC/MUX to inspect the bit pattern while sending an identical NRZ signal through both arms. The Pattern Delay Block, in the FPGA design, contains the pattern of the current 64 parallel processed bits and previous pattern, received from the Pattern Memory Block. By selecting the 64 bits that would be processed out of this sequence of 128 bits we can delay the pattern by up to 5980 ps and achieve 1 bit period (94 ps) synchronization accuracy.
The third and final step is carried out by monitoring the optical signal generated by the MZ and comparing the pattern of each arm with a reference (delivered as a pattern start pulse from the FPGA) and optimizing the BER. We adjust the delay of each arm using an analog delay line in each arm. Achievable accuracy is better than 2 ps. In principle it would be possible to replace the manual steps by an automatic alignment system for the two arms.
4. Transmission results
4.1 Linear transmission
Figure 5 shows the results when operating with an average EPD channel launch power of 0 dBm at the start of each span. Figure 3(a) gives the achieved BER versus OSNR for a LUT with 11 bit address size. BER < 10−9 was achieved for transmission over 452 km, and BER < 10−6 for distances up to 641 km. The maximum transmission distance was limited by the size of the LUT used. The performance of the EPD signal shows a penalty less than 1 dB (for BER < 10−8) up to 450 km. We used an operating point at a BER of 10−6 in the Figs. 5 and 9 representing an optical link operating with a margin compared to the FEC threshold of 2 × 10-3. The eye diagrams presented in Fig. 6 correspond to points on some of the curves in Fig. 5(a) at an OSNR of 18 dB. The eye diagrams were recorded by dividing the recovered clock by a factor of four.
Fig. 5 Transmission result without significant NL effects at 0 dBm launch power, showing (a) the achieved BER versus OSNR for an 11 bit LUT and (b) the requred OSNR versus lengths to achieve a BER of 10−6 for LUTs with different address sizes (7 and 11 bits).
Fig. 6 Eye diagrams with OSNR of 18 dB at the receiver of (a) an uncompensated NRZ signal after 100 km tranmission,compared to EPD NRZ after (b) 100 km, (c) 452 km and (d) 737 km tranmission.
Figure 5(b) shows the comparison of the results with 7 bit LUT and 11 bit LUT based EPD, and also with NRZ without EPD. Only points for 0 and 93 km are present for NRZ without EPD because at 188 km locking of the clock recovery module to the received signal was not possible.
To achieve 7 bit EPD we kept a LUT with 11 bit address size in the electronic design but loaded a table constructed taking only 7 bits in consideration. This gave identical entries in the table for memory addresses where the first 7 bits were identical. As expected, the 452 km limit with 11 bit LUT was reduced to less than 300 km when the LUT address size was reduced to 7 bits, showing that, at this operating point, the memory depth of the LUT table is the limiting factor [7].
It can be seen that there is a penalty between the required OSNR using EPD at distances below the limit imposed by the size of the lookup table (e.g. below 450km for 11 bit LUT) compared to back to back operation with NRZ. This penalty is present because of limited time and amplitude resolution when creating the transmitted signal by DACs and because of non-optimal LUT entries.
Figure 7 shows the degradation of the received signal when the following control parameters in the transmitter are adjusted away from the optimum values: bias voltages for the I and Q inputs of the MZ, quadrature (π/2) control and the signal synchronization between the I and Q arms in the transmitter. Figure 7(a) and 7(b) are for the case of transmission over 452 km with 0 dBm launch power and an OSNR of 17 dB at the receiver. Figure 7(a) shows that keeping the setting within 7% Vπ of the optimal value will limit the penalty to less than a decade of the BER. Two possible mechanisms can be the source for variations in these settings: actual variation in the control voltages (because of imperfect DC sources), or changes in the transmission system (for example, temperature changes within the MZ) requiring adjustment of the optimal setting.
Fig. 7 Influence of non optimal settings at the transmitter on the BER (a)Variation of biases and quadrature (π/2) control, (b) misalignment in time between both arms
In Fig. 7(b) we show the effect of timing misalignment between the two arms driving the MZ. If the misalignment is kept below 12% of the bit period, the penalty on the BER will be less than a decade.
The influence of changing the PkPk levels of the signals driving the arms of the MZ away from the optimal setting is presented in Fig. 8 . The optimal setting being the point at which the combination of the control settings for the of PkPk levels, the biases, quadrature delay and arm delay resulted in the minimal BER at the receiver. This graph was obtained for transmission over 552 km fiber, with 0 dBm launch power and an OSNR of 20 dB at the receiver. The graph is based on 26 measuring points inside the coloured area of the graph, a Kriging based algorithm with minimal smoothing was used for interpolating the points. The minimum achievable BER was 2.5 × 10−8. It can be seen that keeping the PkPk level within 10% Vπ of the optimal limits the penalty to below one decade of BER.
As expected, within certain limits, an inaccuracy in the setting of the PkPk level of one arm can be compensated by optimizing the PkPk level of the other arm. This is indicated by the trough in the plot at an angle to the x and y axis. It is the ratio of the setting of the two arms that is important to maintain a good level of performance, rather than the absolute level of the settings of the arms.
The optimal peak-to-peak voltages driving the MZ were found to correspond to 90% of Vπ on the I input and 105% of Vπ on the Q input. These values are actually larger than those assumed in the calculation of the LUT tables, in which a modulation PkPk value of 30% of Vπ on the I input and 36% of Vπ on the Q input were assumed. However, it can be seen from Fig. 8 that decreasing the PkPk values, while reoptimising all the other control setting to achieve minimal BER to operate at the PkPk levels used in the calculation of the LUT did not improve the achieved BER. We suggest that three elements can explain this. Firstly the value of Vπ was measured on the DC ports of the MZ, and a greater Vπ might be present on the RF ports. Secondly the extreme signal values at which the peak levels are reached and which lie in the non-linear part of the modulation curve do not occur often in the drive signals. Hence, the majority of the samples lie within the linear part of the modulation curve. Thirdly there is a trade-off between maintaining linearity and achieving maximal extinction ratio.
4.2 Nonlinear transmission
Next, higher power transmission experiments were performed on the same link as in the previous Section, to investigate the effect of fiber nonlinearity (NL), and to assess the effectiveness of the SPM compensation. While we did not introduce clipping of the calculated predistorted signal when constructing the LUT contents, driving the signals at the higher then calculated PkPk levels, as mentioned in chapter 4.1, will introduce a form of clipping because of the saturation of the electrical amplifier and the modulation characteristics of a MZ
Figure 9(a) shows the distance penalty when increasing the average launch power. There was a penalty of less than 1 dB when increasing the power of the EPD channel from 0 dBm to + 4 dBm over distances up to 500 km. The transmitter is capable of predistorting the additional NL based signal distortions. When increasing launch power of the EPD channel up to + 8 dBm the performance dropped (at 450 km the OSNR penalty compared to 0 dBm and + 4 dBm launch power was greater than 10dB).
Figure 9(b) shows the performance of LUT based EPD for the case where the entries in the LUT tables are calculated for a particular fixed launch power, while the actual launch power in the link is varied. The points represent the OSNR required to achieve a BER of 10−6. The transmission distance was 452 km and an 11 bit LUT was used. When acquiring the measurement points, we only adjusted the launch power, the variable optical attenuators controlling the added noise, the received power and the decision threshold level. We kept the other control signals (PkPk levels, biases, quadrature (π/2) control) at the values required when optimising at the normal operating point for that particular LUT.
The blue markers show that a link in which the LUT entries are calculated for 0 dBm launch power suffers a decrease in performance when increasing the launch power, while there is no reduction in performance when lowering the power below 0 dBm, showing that it is mainly linear chromatic dispersion that is being corrected and that there is no significant NL effects degrading the signal at 0 dBm. The green markers show the same measurements for the LUT entries calculated for + 4 dBm launch power. In this case we observed a 2 dB reduction in the required OSNR at + 4 dBm, and an increase in required OSNR when lowering the launch power, indicating that the effect of SPM is being successfully compensated.
5. Conclusion
We showed that chromatic dispersion and self-phase modulation compensation using real-time LUT-based digital filtering is possible at 10.7 Gb/s with current commercially available FPGA and DAC/MUX technology.
We designed and constructed an electronic predistortion transmitter that can achieve a BER of 10−6 at an OSNR of 16 dB with an 11 bit LUT for linear transmission over 641 km of uncompensated NDSF.
We found that the choice of digital design tools can make a significant difference in achievable results with a particular FPGA. The size of the LUTs that can be included in the design can vary by a factor of two depending on the synthesis engine used. Further development would allow automatic port and arm synchronization, required for unattended startup (which is expected to be included in new DAC devices [14]).
Characterisation of the sensitivity of the BER in relation to modulator bias, quadrature control and signal misalignment between I and Q modulator drive waveforms were measured, quantifying the accuracy required in the control voltages in the transmitter.
With SPM compensation, it was shown that the transmitter achieves a penalty of less than 1 dB in required OSNR when the launch power was increased from 0 dBm to 4 dBm in transmission over 452 km.
The experience gained in implementing this predistortion transmitter could be used in the future to implement more advanced transmitter-based DSP for other modulation formats (e.g, DPSK, QAM and OFDM) and equalization techniques.
Acknowledgments
The authors would like to acknowledge the financial support of Ericsson, EU FP6 NOBEL2 (Contract No. FP6-IST-027305) programme, the UK Engineering and Physical Sciences Research Council (grant EP/C523865/1) and EU FP7 NoE BONE for this work, as well as support from Micram Microelectronic GmbH, especially Dr. T. Ellermeyer, for the provision of and advice on the use of the DAC/MUX. We would also like to thank Dr H. Griesser and H. Wernz from Ericsson for helpful discussions and advice.
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