1. Introduction

Silica based integrated planar waveguide technology plays an important role in modern optical communication space [1–4]. Commercial products fabricated through this technology include Arrayed Waveguide Grating (AWG) multiplexer and demultiplexer, Mach Zehnder interferometer based Variable Optical Attenuator (VOA), thermo-optical switch, splitters, and more to come. Almost all devices made utilized the “Channel-waveguide” structure. Typically a thick SiO₂ buffer layer is grown on Si substrate, then a core oxide layer is deposited and patterned, before a cladding oxide layer is put on top. The top cladding layer usually has a thickness of 40 µm for the effective confinement of the light in the waveguide core. The cross section of the core waveguide is typically a square shape in the dimension of 8×8 µm2. The index of refraction of this core layer is typically adjusted by doping Ge or P, sometimes a co-doping of B is needed to minimize any stress related effect. The most challenging part of this process is the uniformity requirement across the wafer. The core and cladding layers were usually fabricated through Chemical Vapor Deposition (CVD) process. The CVD technology used in silica planar waveguide technology was established in the Si integrated circuit (IC) fabrication, which has a layer thickness uniformity of about (3–5)% and index of refraction uniformity of the order of 1×10^-4 across an 8-inch wafer. Most of the optical devices have a much larger die size comparing to a typical IC chip, where 5 cm in one dimension is quite common. Above that, most of the optical devices utilize phase properties of light traveling inside the waveguides. Effective optical path is strongly affected by the index of refraction and layer thickness uniformities across a wafer, and varies from run to run. A tight requirement on index uniformity translates into low yield and high cost for silica planar waveguide based devices, which prevents it from being used in access networks, where cost is a very sensitive issue.

For tunable devices, thermo-optic effect is used where a heater sits on top of the waveguide to alter the index of refraction through temperature effect. For channel waveguide, one of its major drawbacks is the high power consumption due to the thick top cladding layer that diverges and resists the heat flowing from the top heater to the core waveguide. For the same reason, the frequency response of Silica thermal based VOA is usually in the milli-second range.

In this paper, we report a new silica planar waveguide structure, where a ridge silica waveguide resides on top of a vacuum gap. The waveguide is grown through high temperature thermal oxidation, which is probably the most uniform and repeatable process considering any Si processing in terms of layer thickness and index of refraction. In addition, this ridge structure provides effective means for supplying heat to the waveguide, so as to reduce power consumption significantly in tunable devices.

 

Fig. 1. Schematic diagrams illustrating the basic ridge waveguide structure and its fabrication process. a) A shallow trench is formed at oxide film surface; b) a ridge structure is formed in oxide film; c) The original wafer α was bonded into a carrier wafer β, with nitride deposited on both sides; d) The nitride and backside oxide of wafer α together with about 400 µm of Si were lapped away. e) A ridge waveguide is encapsulated inside a vacuum cavity, not drawn proportionally. The approximate mode shape is drawn as guide to the eyes. f) The up-side-down positioned ridge waveguide with a cladding layer.

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2. The basic waveguide structure and its fabrication

2.1 Fabrication of a basic waveguide structure

A 10-µm thick thermal oxide was grown on a 6-inch bare Si wafer α at 1150°C in DI vapor environment. This oxide was characterized by a Filmtek 4000 system from Scientific Computing International, Inc (Carlsbad, CA), which had the capability of high-resolution optical index (10^-5) and thickness mapping. The thermal oxide had a thickness average of 10339nm with a standard deviation of 10 nm after evaluating 9 uniformly distributed points on the wafer. The optical index at 1550nm was measured to be 1.445818±1.4×10^-5 for TE mode, and 1.446575±2.8×10^-5 for TM mode.

Firstly, a 1-µm deep shallow trench of 74-µm in width was dry-etched, as displayed in Fig. 1(a); then the ridge waveguide was defined as shown in Fig. 1(b). The depth and width of the ridge were chosen to be 4.5 and 13 µm respectively. Practically the width of the ridge waveguide could be varied as long as the single mode condition could be satisfied. The width of the slab region was chosen to be 12.5 µm on each side to ensure the mode confinement. All silica dry etch was performed using an Applied Materials, Inc (Santa Clara, Ca) Centura 5200 etcher. Secondly, this wafer was attached to a carrier Si wafer β through room temperature wafer bonding [4] under a vacuum of 1×10^-3 Torr with pre-filled N₂, using a EVG 620 precision alignment bonder (EV Group Inc, phoenix, AZ). Annealing of bonded wafers was performed in DI vapor/O₂ environment at 1050 °C for 30-45 mins. After cooling down to room temperature, a 0.3-µm thick low-pressure-chemical-vapor-deposited (LPCVD) nitride was deposited to both sides of the bonded wafer, as depicted in Fig. 1(c). The nitride and oxide on the back of the α wafer together with about 400-µm thick of Si were lapped away using a Logitech PM5 system (Logitech inc, England), as illustrated by Fig. 1(d). The remaining Si was etched in Tetra-Methyl Ammonium Hydroxide (TMAH) bath at 95 °C using bonded oxide layer as an etch stop, while the nitride underneath carrier wafer β worked as an etch-protector. This formed the final structure of Fig. 1(e). The main challenges in this process were the wafer bonding of a very thick oxide and the lapping process. The latter was difficult because as the oxide in the front was removed, and the wafer thickness was reduced during lapping, the stress in the Si substrate went up. Experimentally, we found that a slow lapping of about 35 rpm with a pressure of about 4.8×10³ Pascal was required to avoid chipping and keep a reasonable material removal rate. In the slab region, to reduce the cross talk, the distance between the neighboring channels L was kept at least 60 µm.

2.2 The cladding layer

Practically, a low index cladding material (lower than thermal oxide) is needed on top of the up-side-down positioned ridge waveguide, as displayed in Fig. 1(f), to protect the optical mode from outside disturbance, such as a running metal line. As a starting point, we evaluated several low dielectric constant (low-k) materials used as Interlayer dielectric (ILD) materials in Si CMOS integrated circuit (IC). Their material properties are summarized in Table I. All these films were put on top of the ridge waveguide by spin-coating and follow-up curing.

The material index and absorption were measured by preparing a single coating on Si substrate and tested using Filmtek 4000 (Scientific computing international, Carlsbad, CA). The level of absorption given was actually the upper detection limit of the machine. Here the loss was measured at ultraviolet, visible and near infrared band and estimated at far infrared.

Table 1. Low-index material properties

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The film stability data was obtained by spin-coating of these low-k films onto a Si wafer with a 1-µm thick of thermal oxide. Experimentally, we found that when the low-k cladding thickness went beyond certain value, they would crack after curing. The critical thickness values were summarized in Table I. For all films evaluated, we found that if we let the film sit in the fab for an extensive amount of time, all films eventually crack if we didn’t have an additional capping layer. Therefore further study to stabilize the film is needed.

2.3 Forming the facet

An angled view of the waveguide cross-section near facet under scanning electron microscope (SEM) is displayed in Fig. 2. A top view optical image of the waveguide near facet is shown in Fig. 3(a). Obviously, We need to maintain the vacuum seal during polishing to prevent contamination with polishing slurry places significant demands on polishing accuracy. Practically, there are three ways to overcome this,

1. As shown in Fig. 3 (a), a separate waveguide on vacuum part could be included near the polishing facet. We can still achieve low insertion loss as long as over-polishing does not disturb the main part; the tight polishing requirement is therefore relieved.

2. Under-polish, some length of SiO₂ remains, refer to the part labeled “δ” in Fig. 3(b), sitting on top of Si substrate, which will cause some extra loss.

3. Facet formation by dry etches.

 

Fig. 2. Angled-view scanning electron microscope image of a silica ridge waveguide encapsulated inside a cavity.

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Fig. 3. (a) top view optical image of a silica ridge waveguide sitting on top of a vacuum gap, (b) a schematic diagram of the same structure.

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3. Testing results

Many straight waveguides resemble what was described in Fig. 1(e) with different lengths (17, 40, and 45 mm) were tested without a cladding layer due to the immatureness of the cladding layer and the matching oil was not used. The mode was launched and the light was collected using a generic single-mode fiber. The typical insertion loss (IL, average of TE and TM mode) measured at 1550 nm for a 45 mm long straight waveguide was 1.27 dB. The mode coupling loss could be calculated using mode solver to be 0.42 dB per side. As shown by Fig. 3(b), there is a polishing uncertainty caused extra loss, which could be different for different waveguides. We therefore found more meaningful to use the calculated coupling loss to estimate an upper limit of propagation loss. The waveguide geometries are: total silica thickness H=10 µm, ridge etch depth H1=4.5 µm, and WG width W=13 µm, see Fig. 1(e).

4. Discussions

This new planar lightwave technology used thermal oxide as the optical core material, which has an excellent uniformity in both thickness and optical index. Since both oxidation and Si wet-etch are batch processes, the cost of the waveguide could be lower than the conventional CVD oxide given a reasonable yield could be achieved. Because the cladding of the ridge waveguide (about 1 µm) is considerably thinner than the generic approach (about 20-40 µm), the thermal efficiency is much higher. Thermal simulations were conducted on the Mach-zehnder structures with 5 mm long arms, which were formed using the afore-mentioned ridge waveguide structure, as well as the channel waveguide of an 8×8 µm² cross-section. The latter required 3 times the power to reach π phase shift, and the thermal response time was comparable.

In terms of making more complex structures, like Arrayed Waveguide Gratings (AWG), because of the in-plane compressive stress in the oxide, there might be some limitations: firstly, mechanical buckling restricts the length of a suspended beam under compression; secondly, the bi-fringence effect due to asymmetrical stresses on the TE and TM modes have to be compensated, otherwise the high index uniformity across a wafer achieved by thermal oxidation will not be meaningful. These topics will be addressed in later publications.

5. Conclusions

Some primitive studies on a novel silica ridge waveguide structure were introduced. The main advantage with this technology is the highly uniform silica material and efficient thermal-optical tuning. There are lots of challenges born with this new technology, e.g. forming the facet, and addressing the reliability issue of the cladding layer. We believe this pioneering work has opened lots of opportunities for future study.

Dr. Prakash Koonath from Electrical Engineering, UCLA is acknowledged for the proof-reading of this manuscript.