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Abstract
Highly stable, low phase noise microwave oscillators are essential for various applications. An optoelectronic oscillator (OEO) can overcome the short-term phase noise limitation of pure electronic oscillators at high oscillation frequency. Nonetheless, the long-term frequency stability should be addressed. To stabilize the frequency of OEO, a phase-locked loop (PLL) is widely used to synchronize the OEO to a stable reference. However, due to the narrow free-spectral-range (FSR) of the oscillation cavity of the OEO, the pull-in range of the PLL is limited. It is challenging to acquire phase-locking at startup and phase-relocking when mode-hopping of OEO occurs. Here, by using an automatic frequency calibration (AFC) assisted PLL, we attain a highly stable 10 GHz phase-locked OEO with robust phase-locking at startup and phase-relocking when mode-hopping of OEO occurs, for the first time. With the use of a fast digitally-controlled frequency shifter and a real-time frequency error detection unit in the AFC loop, the phase-locking and phase-relocking time are below 120 ms. Furthermore, it shows the phase noise of −135 dBc/Hz at 10 kHz offset, side-mode suppression ratio (SMSR) of 128 dBc, and Allan deviation of 4.8×10−11 at 5000 s for the phase-locked OEO. We thoroughly investigate the dynamics of the automatic frequency calibration, the phase-locking process, the phase-relocking after OEO mode-hopping, the system under vibration, and the frequency switching. Our approach is promising to generate a highly stable, low phase noise, and determinate frequency microwave signal, which can be used as a low phase noise reference for a microwave frequency synthesizer and high performance sampling clock for a data conversion system.
© 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
Microwave source is a key component for many subjects, such as radar, communication, sensing, test and measurement. It is desirable to offer the high-frequency carrier for radar and wireless communication, the high speed clock for wireline communication, and the local oscillator (LO) for test instrumentation. In particular, the long-term frequency stability and short-term phase noise of microwave source are two crucial metrics for the applications [1]. Photonic-based optoelectronic oscillator (OEO) can overcome the phase noise limitation of pure electronic oscillators at high frequency, which is a good candidate to generate high spectral purity microwave or millimeter-wave signal [2–5]. By using long fiber in the oscillation loop, the OEO shows exceptional short-term phase noise performance. However, due to the dependence of the effective refractive index of the fiber on temperature, the frequency of the OEO drifts with ambient temperature variations [6,7]. Furthermore, the single oscillation mode of OEO is selected by a narrow bandpass RF filter. The center frequency of RF filter is also sensitive to the ambient temperature variations. Due to the narrow mode spacing of OEO, the center frequency drifts of RF filter leads to the mode-hopping of the OEO [6]. These two issues deteriorate the long-term frequency stability of OEO, which limits the use of OEO in practical applications.
To improve the long-term frequency stability of OEO, many approaches have been explored [8–23], such as thermal stabilization [8], injection-locking [10], passive or active phase compensation [11–16], and phase-locking [17–23]. Among them, phase-locking techniques are promising ways to stabilize the OEO to highly stable references via phase-locked loops (PLLs). By setting a limited loop bandwidth of the PLL, the phase-locked OEO can achieve improved long-term frequency stability and maintain high spectral purity at high offset frequencies, simultaneously [6]. The OEO serves as a voltage-controlled oscillator (VCO) in a PLL. The voltage-controlled continuous frequency tuning of OEO is demanded, which can be realized by the use of voltage-controlled RF phase shifter or fiber stretcher in the OEO loop [17]. To acquire phase-locking at startup, the frequency error between reference and OEO should be within the pull-in range of PLL [24,25]. Theoretically, the achievable pull-in range of the PLL is limited by the mode-hop-free continuous frequency tuning range of OEO. Nonetheless, a fundamental issue for the PLL based OEO frequency stabilization still remains, which should be addressed. Due to the long cavity of OEO, it leads to a narrow free-spectral-range (FSR), which limits the mode-hop-free continuous frequency tuning range of OEO. As a consequence, it makes a narrow pull-in range of PLL. However, the 3-dB bandwidth of RF filter is normally larger than the FSR of OEO, which results in many alternative oscillation modes. Due to the unpredictable oscillation mode of OEO after the OEO is powered on, it is challenging to guarantee the frequency error between reference and OEO lower than the pull-in range of PLL, which leads to the difficulty of acquiring robust phase-locking at startup. Besides, the PLL will lose phase-locking when mode-hopping of OEO occurs. Under this case, it is unable to automatically acquire phase-relocking by PLL. These two issues induced by the narrow FSR of OEO greatly deteriorate the robustness of phase-locking acquisition, which remains unresolved.
In this paper, we propose a fast automatic frequency calibration (AFC) assisted PLL to lock the OEO to a stable electrical reference, which can achieve highly stable phase-locked OEO with automatic phase-locking at startup and phase-relocking when mode-hopping occurs. Due to the use of fast digitally-controlled frequency shifter and real-time Fast Fourier Transform (FFT) based frequency error detection unit in the AFC loop, the frequency error between OEO and reference can be rapidly calibrated to be within the pull-in range of the PLL. The phase-locking and phase-relocking time are measured to be below 120 ms. The repeatability of automatic phase-locking at startup is tested. Besides, due to the capability of automatic acquisition of phase-relocking after mode-hopping of OEO, the system can keep the phase-locked state during a testing time beyond 10 hours. By setting the loop bandwidth of the PLL to 400 Hz, we attain a 10 GHz microwave signal with high long-term stability and low phase noise, simultaneously. It shows the single-sideband (SSB) phase noise of −135 dBc/Hz at 10 kHz offset, side-mode suppression ratio (SMSR) of 128 dBc, and Allan deviation of 4.8×10−11 at 5000 s for the generated microwave signal. To test the capability of phase correction of the PLL, the transient frequency and phase responses of the phase-locked 10 GHz signal under the environmental vibration are measured. It shows that the PLL can recover phase-locked state within 0.2 s. Furthermore, due to the use of AFC loop, the frequency switching of the system within the frequency calibration range is also evaluated. The frequency switching resolution can be 16 Hz. Our approach is promising to achieve a phase-locked OEO with high long-term frequency stability, determinate target frequency locking, low phase noise, low spurs, high frequency accuracy, automatic operation and high robustness, simultaneously.
The remaining paper is organized as follows. In Section 2, the system architecture and operation principle of our proposed AFC aided phase-locked OEO are presented. After that, based on the proposed scheme, experimental setup and results are shown in Section 3. Finally, a conclusion is drawn in Section 4.
2. System architecture and operation principle
In the following sub-sections, we will firstly show the issues of the frequency stabilization of an OEO by using a PLL without the assistance of frequency calibration. To solve these issues, we will propose an AFC assisted PLL to stabilize the frequency of OEO. The system architecture and operation principle will be presented.
2.1 Issues of the frequency stabilization of OEO via a PLL
Figure 1 shows the basic architecture of a PLL to stabilize the frequency of OEO. In this configuration, the OEO serves as a VCO in the PLL. The ability of voltage-controlled continuous frequency tuning of the OEO is demanded. To make the PLL acquire phase-locking at startup, the frequency error between reference and OEO should fall in the pull-in range of the PLL. Theoretically, the pull-in range of the PLL is limited by the continuous frequency tuning range of the VCO, which is the continuous frequency tuning range of OEO in this case. It makes the continuous frequency tunability of the OEO as a critical property for the frequency acquisition of the PLL at startup. The larger the continuous frequency tuning range, the easier to acquire phase-locking. Basically, the continuous frequency tuning capability of the OEO can be achieved by changing the RF phase delay of the oscillation cavity. To investigate the maximum mode-hop-free continuous frequency tuning range of OEO, we will show the theoretical analysis in the following part.
Fig. 1. Basic architecture of the frequency stabilization of OEO by a PLL. foeo and fref are the frequencies of the OEO and reference, respectively. ESA: electrical spectrum analyzer.
According to the Barkhausen criterion, the loop phase of the OEO cavity should be a multiple of 2π at the selected oscillation mode [1]. Mathematically, it can be expressed as:
where f0 is the nominal frequency of the free-running OEO, τd is the time delay of the oscillation cavity, k is the selected oscillation mode number. When the RF phase delay variation is applied in the OEO cavity, the loop phase condition is changed to: where Δf is the frequency change of the OEO which induced by the RF phase delay variation of the OEO cavity, ΔφRF is the RF phase delay variation of the OEO cavity. To avoid mode-hopping of OEO, the maximum range of the RF phase delay variation is limited to 2π. By substituting Eq. (1) to Eq. (2), the frequency change of the OEO can be derived as:Note that 1/τd is the mode spacing of the OEO. From Eq. (3), it shows that the mode-hop-free continuous frequency tuning range is limited to the mode spacing of the OEO. Usually, a long loop length is needed to reduce the close-in phase noise of the OEO. However, a long loop length results in a narrow mode spacing. It limits the pull-in range of the PLL. A narrow pull-in range makes it challenging to acquire phase-locking after the OEO is powered on and the mode-hopping of OEO occurs, which will be illustrated below.
Figures 2(a) and 2(b) show the schematic diagrams of phase-locking processes in frequency domain after the OEO is powered on and the mode-hopping of OEO occurs, respectively. In an OEO, an electrical bandpass filter (EBPF) is used to select the oscillation mode. The characteristics of the passband for the EBPF are depicted by the blue dotted curves in Figs. 2(a) and 2(b). Normally, the 3-dB bandwidth of the EBPF is much larger than the mode spacing of the OEO. It results in many alternative oscillation modes inside the passband, as shown by discrete oscillation modes in Figs. 2(a) and 2(b). Due to the variations of ambient temperature, supply voltage and the environmental vibration, it is hard to select a deterministic oscillation mode after turning the OEO on. Any of the oscillation mode inside the passband of the EBPF can become the final survive mode. From the previous analysis, the pull-in range of PLL is limited to the mode spacing of the OEO, which is smaller than the passband of the EBPF. If the frequency difference of the initial oscillation mode and the reference is larger than the pull-in range, the PLL may never acquire phase-locking, as depicted in Fig. 2(a). Assuming that the PLL acquires phase-locking at startup, the mode-hopping will make the PLL lose phase-locking, as shown in Fig. 2(b). A worst situation is that the PLL may never acquire phase-locking again. These two issues make it hard to achieve a robust phase-locked OEO.
Fig. 2. Schematic diagrams of the phase-locking processes in a phase-locked OEO. (a) The process after powered on. (b) The process after mode-hopping. foeo, fref and funlocked are the frequencies of the free-running OEO, reference, and the OEO after mode-hopping.
2.2 System architecture of the proposed AFC aided phase-locked OEO
To solve the issues induced by the narrow pull-in range of the PLL, we propose an AFC loop to achieve fast automatic frequency acquisition for the phase-locked OEO. Figure 3 shows the conceptual architecture view of the system. It includes two loops, which are the AFC loop and the frequency-multiplying PLL. The key component of the system is the frequency-shifted OEO, which is formed by the analog mixing of the outputs of a free-running OEO and a DDS. The combination of DDS and RF mixer serves as a digitally-controlled frequency shifter to rapidly calibrate the frequency of the OEO. To maintain the coherency between the outputs of DDS and OEO, we use the Integer-N frequency division of the OEO as the sampling clock of the DDS. Besides, due to the low phase noise of the OEO, the sampling clock contributes low additive phase noise to the output of the DDS. The outputs of the OEO and the DDS are mixed through a double-balanced microwave mixer. Two tones can be generated, which are the sum frequency and difference frequency terms. Due to the nonlinearity of the microwave mixer, harmonics and the spurs of the DDS, some spurious exist at the output of the microwave mixer. To achieve a single tone at the output of microwave mixer, we use an EBPF with high frequency selectivity to select the sum or difference frequency term. In our configuration, we select the difference frequency term as the output. In our previous work [26], we have derived the frequency of the analog mixing of the OEO and DDS. The frequency of the frequency-shifted OEO can be expressed as:
Fig. 3. System architecture of the proposed AFC aided phase-locked OEO. PFD: phase-frequency detector. EBPF: electrical bandpass filter. DDS: direct digital synthesizer. ADC: analog-to-digital converter. FPGA: field-programmable gate array. ESA: electrical spectrum analyzer. MFD: microwave frequency divider. VCO: voltage-controlled oscillator. M, N: the frequency division factor of the microwave frequency dividers.
With the aid of the AFC loop, the phase-locking processes after the OEO is powered on and the mode-hopping of OEO occurs are illustrated in Figs. 4(a) and 4(b), respectively. Due to the use of frequency-multiplying PLL, the target locking frequency is the multiplication of the frequency division ratio of MFD and the frequency of the reference oscillator. At startup, if the frequency error between target locking frequency and frequency-shifted OEO is not in the pull-in range of the PLL, the AFC loop will estimate the frequency error, and calibrate the frequency of the frequency-shifted OEO to make the frequency error within the pull-in range of the PLL for the first step. After the frequency calibration, the PLL will acquire phase-locking for the second step. Assuming that the frequency-shifted OEO is already phase-locked to the reference, as shown in Fig. 4(b). If the mode-hopping of OEO occurs, the PLL will lose phase-locking, as illustrated as the first step. Thanks to the using of the AFC loop, the frequency error detection unit will detect the event of out of lock and automatically calibrate the frequency of the frequency-shifted OEO to make frequency error within the pull-in range of the PLL in the second step. Finally, the PLL can acquire phase-relocking in the third step. With the assistance of AFC, the system can automatically achieve phase-locking.
Fig. 4. (a) and (b) Schematic diagrams of the frequency calibration and phase-locking processes of the AFC aided phase-locked OEO after powered on and mode-hopping, respectively. ffs_oeo, fref and funlocked are the frequencies of the frequency-shifted OEO, reference, and the frequency-shifted OEO after mode-hopping.
3. Experimental results and discussion
In order to verify our scheme, an experiment is implemented. Figure 5 shows the experimental setup. The setup consists of three parts. The first part is the frequency-shifted OEO, the second is the frequency-multiplying PLL, and the third one is the AFC loop. To achieve single mode oscillation, we use dual-loop structure OEO. A continuous-wave laser (Teraxion Inc., NLL) with wavelength of 1550.12 nm, and output power of 80 mW is used as the light source of the OEO. A dual-output Mach-Zehnder intensity modulator (DOMZM, Eospace Inc., AX-1 × 2-0MVS-40-PFU-SFU) with bandwidth of 40 GHz is utilized to realize the electro-optical conversion. The length of the short and long single-mode fibers (SMFs) are 0.1 km and 2 km, respectively. Two photodiodes (Finisar Inc., HPDV2120R) with bandwidth of 50 GHz are used to convert the optical signals to electrical signals. An analog RF phase shifter (RF-Lambda Inc., RVPT0818GBC) with RF phase tuning range beyond 360 degrees is inserted in the long loop to achieve voltage-controlled frequency tunability of the OEO. The outputs of the electrical signals from two fiber links are combined by a 3-dB electrical coupler. Two low phase noise amplifiers (Marki Inc., APM-6848) with operation frequency range from 2 GHz to 28 GHz, and single stage gain of 20 dB are cascaded to provide sufficient loop gain for the OEO. A home-made microwave cavity bandpass filter (EBPF1) with center frequency of 10.1 GHz and 3-dB bandwidth of 3 MHz is used to select the oscillation mode of the OEO. By using an electrical coupler (EC3), a portion of the output of the OEO is send to a divide-by-10 microwave frequency divider (MFD, RF Bay Inc., FBS-10-40). The output of the MFD is served as the sampling clock of the DDS (Analog Devices Inc., AD9910). By programming the frequency control word of the DDS via FPGA (Xilinx Inc., Zynq XC7Z100-2FFG900I), we set the frequency of the output of DDS to 100 MHz. After mixing the outputs of the 10.1 GHz OEO and the 100 MHz DDS via the mixer (Marki Inc., M1-0212), a 10 GHz RF signal is achieved. To suppress the spurious, we use a home-made microwave cavity filter (EBPF2) with center frequency of 10 GHz and 3-dB bandwidth of 6 MHz after the mixer. The generated 10 GHz RF signal is the output of the frequency-shifted OEO. To stabilize the frequency of the frequency-shifted OEO, a frequency-multiplying PLL is used. To satisfy the operation frequency range (10 MHz to 1.3 GHz) of the PFD (Analog Devices Inc., HMC4069), the output of the frequency-shifted OEO is frequency divided by a divide-by-8 MFD (Analog Devices Inc., HMC862A) before feeding into the VCO input port of PFD. Besides, the PFD has an internal programmable frequency divider. We set the frequency division factor of the internal frequency divider to 2. The reference of the PLL is formed by a microwave synthesizer (Keysight Inc., E8257D) with frequency of 625 MHz. Hence, the target locking frequency for the PLL is 10 GHz. The PFD compares the phase and frequency of the reference and the feedback frequency divided frequency-shifted OEO, which can produce an error voltage at the Error output port of PFD. This error voltage is sent to a home-made third-order active proportional-integral (PI) loop filter. The output of the loop filter is applied on the control port of VCP to form a PLL. The PFD also has a lock detection output, which includes the information of the frequency difference between the target locking frequency and the frequency-shifted OEO. The output of lock detection port of PFD is captured by an ADC (Analog Devices Inc., AD9238). The captured data is processed by a FPGA after the ADC to detect the frequency error between the frequency-shifted OEO and 10 GHz target locking frequency. After the frequency error detection, the FPGA generates a frequency control word for the DDS to calibrate the frequency error. A phase noise analyzer (Rohde & Schwarz Inc., FSWP26) is used to measure the phase noise of the RF signal.
Fig. 5. Experimental setup of the proposed AFC assisted phase-locked OEO. DOMZM: dual-output Mach-Zehnder intensity modulator. PD1, and PD2: photodiodes. VCP: voltage-controlled RF phase shifter. EC1, EC2, and EC3: electrical couplers. LPA: low phase noise amplifier. EBPF: electrical bandpass filter. DDS: direct digital synthesizer. PFD: phase-frequency detector. ADC: analog-to-digital converter. FPGA: field-programmable gate array.
3.1 Characteristics of spurs and frequency tunability of the frequency-shifted OEO
Figures 6(a) and 6(b) show the electrical spectra of the frequency-shifted OEO with spans of 26.5 GHz and 300 kHz, respectively. The power of the carrier is around −8 dBm. The second harmonic suppression ratio is beyond 40 dBc. Besides, due to the use of 2 km single-mode fiber in the OEO, the mode spacing is around 100 kHz. From Fig. 6(b), the power of the side-modes around the carrier are lower than −115 dBm. It results in the SMSR higher than 107 dBc. These metrics show the low spurs of the frequency-shifted OEO. To investigate the frequency tunability of the frequency-shifted OEO, we measured the continuous frequency tuning via RF phase shifter and coarse frequency tuning via DDS, as shown in Figs. 6(c) and 6(d). The control voltage of the VCP is changed from 1 volt to 7 volts. The frequency is continuously tuned from 9.99997 GHz to 10.00003 GHz, as shown by the blue curve in Fig. 6(c). The tuning range is around 60 kHz, which is smaller than the mode spacing of the OEO. Correspondingly, the voltage-controlled frequency sensitivity is around 10 kHz/V, as shown by the red curve in Fig. 6(c). By programming the frequency control word of the DDS via FPGA, we can realize wide frequency tuning of the frequency-shifted OEO, as shown in Fig. 6(d). The frequency sweeping range can be software-defined, which is only limited by the 3-dB bandwidth of the EBPF after the mixer. In our system, the sweeping range can be up to 6 MHz.
Fig. 6. (a) and (b) Electrical spectra of the 10 GHz frequency-shifted OEO with observation spans of 26.5 GHz and 300 kHz, respectively. (c) The frequency and voltage-controlled frequency sensitivity of the frequency-shifted OEO versus the control voltage of the VCP. (d) Characteristics of the frequency tuning of the frequency-shifted OEO via DDS.
3.2 Dynamics of the frequency calibration and phase-locking of the system
To test the effectiveness of the AFC for the automatic frequency acquisition in a phase-locked OEO, we make a comparison of the system with and without the use of AFC. Here, we use two frequency calibration schemes, one is the frequency sweeping method, the other is the fast frequency estimation method based on FFT. The frequency sweeping method will detect the phase-locking status of the PLL. If the PLL is out of lock, the FPGA will periodically change the frequency control word of the DDS to make a frequency sweeping of the frequency-shifted OEO. Once the frequency error between the 10 GHz target frequency and frequency-shifted OEO falls in the pull-in range of the PLL, the PLL can acquire phase-locking. The AFC will stop frequency sweeping once the PLL achieves phase-locking. The frequency sweeping step should be smaller than the pull-in range of the PLL. Due to the use of PFD as the phase detector, the pull-in range of the PLL can be up to the continuous frequency tuning range of the frequency-shifted OEO [25]. We set the frequency sweeping step to 20 kHz, which is smaller than the pull-in range of the PLL. Besides, to maintain enough time for the acquisition of phase-locking of the PLL, the time step of the frequency sweeping should be larger than that of the phase-locking time of the PLL. These two conditions results in a long frequency calibration time. To reduce the time to achieve phase-locked state, we use a fast frequency estimation method, which directly calculates the frequency difference between the 10 GHz target frequency and frequency-shifted OEO by a real-time FFT implemented in a high speed FPGA. After the detection of frequency error, the FPGA will control the DDS to compensate for the frequency error to make the PLL acquire phase-locking. Due to the high speed, parallel computing of the FPGA, the frequency error can be rapidly estimated. It strongly reduces the frequency acquisition time of PLL. Note that a high frequency resolution of the FFT should be maintained to precisely calibrate the frequency of the frequency-shifted OEO to the pull-in range of the PLL.
Figures 7(a) and 7(b) show the transient responses of frequency for the phase-locking at startup with and without AFC by using two frequency error calibration methods. Note that when the system is power down, the measured frequency is invalid. Without the aid of the AFC loop, the PLL will never acquire phase-locking after the system is powered on, as shown by the blue curves in Figs. 7(a) and 7(b). It is caused by the frequency error larger than the pull-in range of PLL. However, with the use of AFC loop, the frequency of the frequency-shifted OEO will be automatically calibrated to make the frequency error within the pull-in range of the PLL. After that, the PLL will acquire phase-locking, as shown by the red curves in Figs. 7(a) and 7(b). The transient time of the system from the out of lock state to the phase-locked state is the sum of the frequency calibration and phase-locking time, which are estimated to be 7.5 s and 80 ms by using frequency sweeping method and fast frequency estimation method, respectively. It indicates that the speed of the FFT based frequency calibration is much faster than that of the frequency sweeping method. Note that the calibration time of the FFT method is influenced by the sampling points used for FFT. With a shorter fiber used in the path where the VCP is located will lead to a larger pull-in range of PLL, which can reduce the required frequency resolution of the FFT. In this case, it lowers the number of the required sampling points for the frequency error detection, which results in a shorter frequency calibration time. Besides, to investigate the dynamics of the phase-locking process of the PLL, we measured the transient response of the frequency. We set the frequency deviation of frequency-shifted OEO relative to 10 GHz target locking frequency within the pull-in range of the PLL. Under this condition, the PLL will automatically acquire phase-locking, as shown by the red and blue curves. With larger loop gain, the phase-locking time will be decreased. Theoretically, the loop gain of the PLL is determined by the gain of the PFD, voltage gain of the loop filter and the frequency sensitivity of the voltage-controlled frequency tunable OEO. The frequency sensitivity of the voltage-controlled frequency tunable OEO can be increased by using a fiber with shorter length in the path where the VCP is located, which will lead to the reduction of the phase-locking time of the PLL. Figure 7(d) shows the electrical spectrum of the phase-locked 10 GHz RF signal with a span of 10 kHz and a RBW of 10 Hz. Besides, to make a comparison, we also measured the electrical spectrum of the free-running 10 GHz RF signal, as shown by the red curve in the inset of Fig. 7(d). Compared with the free-running 10 GHz signal, the noise close to the carrier of the phase-locked signal is strongly suppressed.
Fig. 7. (a) and (b) Frequency calibration and phase-locking processes of the system with and without AFC after powered on by using frequency sweeping method and FFT based fast frequency estimation method, respectively. (c) Transient responses of the phase-locking with different PLL loop gains. (d) Electrical spectrum of the phase-locked 10 GHz RF signal. Inset: electrical spectrum of the 10 GHz free-running frequency-shifted OEO.
The repeatability of the phase-locking of the system with different initial frequencies of the frequency-shifted OEO is tested. The system aims to lock the frequency of the frequency-shifted OEO to 10 GHz. Figures 8(a) and 8(b) show the frequency calibration and phase-locking processes by using frequency sweeping method and fast frequency estimation method for the AFC, respectively. With different frequency deviations between 10 GHz and frequency-shifted OEO at startup, it shows the PLL can acquire repeatable phase-locking when assisted by the AFC loop with either frequency calibration method. The frequency calibration range of the AFC can be up to 6 MHz, as shown in Fig. 8(b). The frequency calibration range is larger than the passband of the EBPF in the OEO loop, which guarantees the robust acquisition of phase-locking with random mode selection of the OEO at startup. Besides, due to the polarity ambiguity of the estimated frequency error by using FFT, it needs to determine the polarity of the frequency calibration. Here, we propose a simple algorithm. In the first step, the frequency calibration process will decrease the frequency of the frequency-shifted OEO by the absolute value of the detected frequency error. After that, if the updated frequency error is within the pull-in range of PLL, the system can acquire phase-locking, which are the cases shown by the curves of a and b in Fig. 8(b). In contrast, if the frequency error is enlarged twice after the first step, then the system will increase the frequency of the frequency-shifted OEO by the absolute value of the detected frequency error. After that, the calibrated frequency error will fall in the pull-in range of the PLL. Finally, it leads to the acquisition of phase-locking, which are the cases shown by the curves of c-f in Fig. 8(b).
Fig. 8. (a) Transient responses of the frequency when the system is powered on with the AFC by using frequency sweeping method. (b) Transient responses of frequency when the system is powered on with the AFC by using fast frequency estimation method.
To investigate the acquisition of phase-relocking of the system when mode-hopping of OEO occurs, we measured the output frequency by a frequency counter (Keysight Inc., 53220A) with a long testing time. The time interval of the frequency counter is set to 10 ms. Due to the bandwidth limitation of the frequency counter, the 10 GHz phase-locked RF signal is frequency down-converted to a 10 MHz intermediate frequency (IF) signal. We captured the frequency of the 10 MHz IF by 200 k points, which corresponds to the measurement time of 2000 seconds, as shown in Fig. 9. Figures 9(a) and 9(b) show the measured frequency of the frequency down-converted 10 MHz signal by using the frequency sweeping method and fast frequency estimation method for the AFC, respectively. During the measurement time of 2000 seconds, the event of mode-hopping occurs for both of the methods. The PLL loses phase-locking due to the mode-hopping. The event of mode-hopping triggers the AFC to calibrate the frequency deviation of the frequency-shifted OEO relative to 10 GHz within the pull-in range of the PLL, which makes the PLL acquire phase-relocking. Due to the mode-hopping, the frequency jump of the system by using the frequency sweeping method is around 300 kHz, which is approximate to the 3 times of the mode spacing of the OEO. The setting time of the mode-hopping is around 200 ms. The frequency calibration time is about 2.6 s. In contrast, the maximum frequency jump of the system by using the fast frequency estimation method is around 20 kHz, which is much lower than that of the system by using the frequency sweeping method. It is caused by the calibration time of the system by using fast frequency estimation method is much lower than the setting time of the mode-hopping. The frequency of the OEO can be calibrated before the jump of the OEO to another oscillation mode. It results in a small frequency jump of the system by using the fast frequency estimation method.
Fig. 9. Frequency measurement of the phase-locked OEO to monitor the mode-hopping and the acquisition of phase-relocking. (a) The measured frequency for frequency sweeping method. (b) The measured frequency for fast frequency estimation method.
3.3 Transient responses of frequency and phase under the vibration
The environmental vibration also has great influence on the frequency stability of the OEO. To test the impact of the environmental vibration on the system, we measured the transient responses of frequency and phase of the 10 GHz signal with vibration on the fiber, as shown in Figs. 10(a) and 10(b), respectively. By applying an abrupt hit on the fiber spools, the frequency and phase experience rapid changes. The instantaneous frequency and phase changes are up to 30 kHz and 2π, respectively. Due to the phase correction of the PLL, the frequency is automatically recovered to 10 GHz within 0.2 s. It indicates that the phase-locked OEO can immune to environmental vibration.
Fig. 10. (a) and (b) Transient responses of the frequency and phase under the environmental vibration, respectively.
3.4 Frequency switching characteristic
Due to the use of AFC, the frequency of the phase-locked signal can be switched within the frequency calibration range of the AFC. Figure 11(a) shows the frequency switching characteristics by changing the frequency of the reference. The blue curve shows the frequency of the phase-locked OEO is switched from 10 GHz to 9.9984 GHz. In contrast, the red curve indicates the frequency is switched from 9.9984 GHz to 10 GHz. Due to the use of the fast frequency estimation method for the AFC, the frequency switching time is less than 100 ms. Besides, we also evaluate the capability of the frequency tuning of the output with high resolution. Theoretically, the tuning step of the phase-locked output signal is determined by the multiplication of the frequency tuning resolution of the reference and the frequency division ratio of frequency dividers in the PLL. By changing the frequency of the reference with 1 Hz step, the tuning step of the phase-locked output is 16 Hz, as shown in Fig. 11(b). It indicates that high resolution frequency tuning can be achieved within the frequency calibration range of AFC loop.
Fig. 11. (a) The frequency switching of the phase-locked OEO. (b) The characteristics of the high resolution frequency tuning of the phase-locked OEO.
3.5 Phase noise and frequency stability of the system
To precisely characterize the power spectral density (PSD) of the SSB phase noise of the phase-locked 10 GHz microwave signal, we use a high sensitivity phase noise analyzer (Rohde & Schwarz Inc., FSWP26) with a cross-correlation method. The measured phase noise results are illustrated in Fig. 12(a). The black, red, blue, magenta, olive, and navy curves show the SSB phase noise of the free-running 10.1 GHz OEO, the 1.01 GHz sampling clock for DDS, the 100 MHz output of DDS, the 10 GHz frequency-shifted OEO, the phase-locked 10 GHz signal, and the 625 MHz reference. It shows the SSB phase noise of −110 dBc/Hz at 1 kHz offset and −137 dBc/Hz at 10 kHz for the 10.1 GHz free-running OEO. There are some spurs at integral multiples of 100 kHz and 1 MHz, which are induced by the side-modes of the dual-loop OEO. Note that the highest level of the side-mode is below −120 dBc, which shows the characteristics of low spurs of the OEO. Due to the frequency division of the 10.1 GHz OEO, it exhibits extremely low phase noise of 1.01 GHz signal. The 1.01 GHz signal is used as the sampling clock of the DDS. With this low phase noise sampling clock, it guarantees high spectral purity of the 100 MHz output of the DDS. By analog mixing the outputs of the 10.1 GHz OEO and DDS, a low phase noise 10 GHz carrier for the frequency-shifted OEO can be generated. In this case, the phase noise of the 10.1 GHz OEO, residual phase noise of the DDS, and residual phase noise of the mixer will contribute to the phase noise of the 10 GHz carrier. With offset frequency below 10 kHz, the phase noise of the 10 GHz signal coincides with that of the 10.1 GHz signal, which is determined by the OEO. However, with offset frequency from 10 kHz to 200 kHz, the phase noise of the 10 GHz signal agree well with the phase noise of the output of DDS, which is dominated by the residual phase noise of the DDS. Due to the conversion loss of the mixer, it raises the phase noise floor of the 10 GHz signal from 200 kHz to 10 MHz offset. To optimize the phase noise performance of the 10 GHz signal, a low residual phase noise DDS and a low conversion loss of the mixer are preferred. As a consequence, with the use of the AFC and PLL, the 10 GHz signal can be synchronized to the 625 MHz reference. The loop bandwidth of the PLL is estimated to 400 Hz. Within the loop bandwidth, the phase noise of the phase-locked 10 GHz is strongly suppressed when compared with the free-running 10 GHz signal. It is determined by the reference. Theoretically, due to the frequency multiplication of the reference by 16, it will raise the phase noise of the reference by 20·log10(16)≈24 dB to the phase noise of the phase-locked 10 GHz output. However, the difference between the experimental phase noise of the phase-locked OEO and the reference is larger than 24 dB, which might be induced by the residual noise of the PFD, MFD and the loop filter used in PLL. Beyond loop bandwidth, the PLL has no phase correction to the free-running 10 GHz signal. It makes the phase noise of the frequency-shifted OEO remain at the output of the phase-locked 10 GHz signal.
Fig. 12. (a) SSB phase noise of the free-running OEO, the sampling clock of DDS, the frequency-shifted OEO, the phase-locked 10 GHz signal, the 625 MHz reference, and the E8257D with frequency of 10 GHz. (b) The Allan deviation of the phase-locked OEO and commercial microwave synthesizer.
To make a comparison, the phase noise of the benchtop microwave synthesizer (Keysight Inc., E8257D) with frequency of 10 GHz is measured, as shown by the orange curve in Fig. 12(a). With the offset frequency range from 600 Hz to 1 MHz, the phase noise of the phase-locked OEO is better than that of the E8257D. Besides, within the loop bandwidth of the PLL, the phase noise of the phase-locked OEO is higher than that of the E8257D, which can be further reduced by optimizing the residual noise performance of the PLL. However, the phase-locked OEO is promising to achieve a higher frequency signal with the phase noise independent of oscillation frequency at the offset frequency beyond loop bandwidth, which is a challenge for pure electronic based microwave signal generator. In addition to the short-term phase noise, the long-term frequency stability is also a key metric for the microwave signal. The long-term frequency stability can be characterized in the time domain by Allan deviation. To calculate the Allan deviation, we use a high precision frequency counter (Keysight Inc. 53220A) to measure the frequency fluctuations of the phase-locked 10 GHz signal. Due to the bandwidth limitation of the frequency counter, the 10 GHz RF signal is frequency down-converted to a 10 MHz IF signal via a 10.01 GHz LO. The LO is generated by a commercial microwave signal synthesizer (Keysight Inc., E8257D). The time interval of the captured points of the frequency counter is set to 100 ms. We tested the system with a time up to 10 hours, which includes 360 k frequency points. With the capability of automatic acquisition of phase-relocking, the OEO can keep the phase-locked state during the 10 hours testing time. The calculated Allan deviation for the phase-locked 10 GHz signal is illustrated by the red curve in Fig. 12(b). The averaging time is from 0.1 ms to 6000 s. At an averaging time of 5000 s, the Allan deviation is on the order of 10−11. It indicates the high long-term frequency stability of the generated 10 GHz microwave signal. Due to the frequency down-conversion for the measurement, the LO may have an influence on the result of the Allan deviation. To make a comparison, we also measured the frequency fluctuations of the analog mixing of two identical commercial microwave synthesizers (Keysight Inc., E8257D). The calculated Allan deviation for the LO is shown by the blue curve. It shows the Allan deviation of the LO is lower than that of the phase-locked 10 GHz signal, which indicates a low influence of the LO on the Allan deviation measurement of the phase-locked 10 GHz signal. Note that the long-term frequency stability of the phase-locked 10 GHz signal is comparable with that of the E8257D. By using a reference with higher long-term frequency stability, such as the microwave atomic clock, the long-term stability of our proposed phase-locked OEO can be further improved.
4. Summary
In summary, a highly stable, low phase noise microwave generation based on an AFC aided phase-locked OEO has been proposed and experimentally demonstrated. It addresses the issue of pull-in range limitation of PLL due to the narrow FSR of OEO. Thanks to the use of a fast digitally-controlled frequency shifter formed by DDS and a FFT based real-time frequency error detection in the AFC loop, it enables rapid frequency calibration of the OEO with an enlarged frequency compensation range to assist the frequency acquisition of PLL. The PLL can automatically acquire robust phase-locking at startup and phase-relocking when mode-hopping of OEO occurs in a short time. Besides, by integrating the butterfly packaged laser, modulator, photodetectors, DC source and the electronic devices used in the PLL and AFC loop on a printed circuit board (PCB), it is promising to make our proposed system as a compact module, which can reduce the size, weight and power consumption. Due to the determinate frequency microwave generation with high long-term frequency stability and low phase noise simultaneously, it is promising to be used as the reference for high performance microwave frequency synthesizer [27], and sampling clock for high speed, low noise data conversion system [28]. Furthermore, as the OEO’s phase noise nearly independent of frequency, it has great potential to generate a millimeter-wave signal with low phase noise and high long-term stability.
Funding
National Key Research and Development Program of China (2018YFB2201704); National Natural Science Foundation of China (61690194, 61805003).
Acknowledgments
The authors would like to thank Rohde & Schwarz for offering the phase noise analyzer (FSWP26).
Disclosures
The authors declare no conflicts of interest.
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