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High sensitivity microwave phase noise analyzer based on a phase locked optoelectronic oscillator

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Abstract

Phase noise is a key parameter to evaluate the short-term stability of a microwave oscillator. This metric is of major concern for many applications. A phase locked loop (PLL) is widely used to extract the phase noise. However, due to the limitation of the phase noise of the reference, it is still a technical challenge to precisely characterize the phase noise of a high frequency carrier. To address this issue, we propose a high sensitivity microwave phase noise analyzer by using a photonic-based reference. By combining an optoelectronic oscillator (OEO) and a direct digital synthesizer, we achieve a 9 GHz to 11 GHz frequency tunable reference with phase noise of −140 dBc/Hz at 10 kHz offset, side-mode suppression ratio of 128 dB, and frequency switching time of 176 ns. Thanks to this low phase noise reference, we attain an X-band phase noise analyzer with an excellent sensitivity of −139 dBc/Hz at 10 kHz offset without cross-correlation. This is the first time to realize a PLL-based phase noise analyzer utilizing an OEO. We thoroughly present a theoretical analysis of our proposed system. Benefiting from the OEO’s phase noise independent of frequency, the operation frequency of our proposed system can be extended to the millimeter-wave range while maintaining high sensitivity.

© 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

1. Introduction

The microwave source is a key device in many applications, such as communication, radar, remote sensing, and test equipment. It is desirable to offer high-frequency carrier for the wireless communication and radar, high speed clock for the wireline communication, and local oscillator (LO) for the test instrumentation. Particularly, the phase noise of the microwave source has great influence on the performance of these applications. To precisely characterize the phase noise of the microwave source, a phase noise analyzer with high sensitivity is required. Typically, there are four ways to realize the phase noise measurement [1,2]. The first one is direct spectrum technique, the second is the discriminator method [3], the third one utilizes the phase locked loop (PLL) technique [4], and the fourth approach is based on a digital frequency modulation (FM) demodulator [2]. By using a spectrum analyzer, it is not capable of separating the amplitude and phase noise. The discriminator method uses self-homodyne demodulation to extract the phase noise of signal under test (SUT). The reference is not needed. Nevertheless, an electrical delay line with long time delay should be used to improve the sensitivity at low Fourier offset frequency. It induces large insertion loss, which rapidly decreases the sensitivity. The PLL technique utilizes direct-homodyne detection. It needs a reference with the same frequency and quadrature phase of the SUT. The digital FM demodulator based method uses direct-heterodyne detection. A reference is also needed to frequency down-convert the SUT to an intermediate frequency (IF). Both the PLL technique and digital FM demodulator based method require the phase noise of the reference much lower than that of the SUT. Theoretically, the sensitivities of these two ways are determined by the phase noise of the reference and the background noise [1]. However, it is challenging to acquire a high frequency reference with low phase noise via electronic oscillators [5], which limits the sensitivity at high frequency carrier. Although the two-channel cross-correlation technique can eliminate the phase noise of the reference and the background noise, which improves the sensitivity of the system [1,6]. It requires two identical single-channel systems, which makes the system cost and complex. Besides, the measurement speed suffers when increasing the number of correlations. In some cases, cross-spectral collapses will occur, which makes the measurement results incorrect [6,7]. Therefore, it is of great significance to improve the phase noise sensitivity of the single-channel of the phase noise measurement system.

Recently, photonic techniques are introduced to develop microwave or millimeter-wave phase noise analyzers [8–12]. In [8], a photonic-delay line is used as a frequency discriminator for phase noise measurement. Compared with an electrical-delay line, it reduces insertion loss and increases time delay, which results in the improvement of the sensitivity at close-in offset frequency. However, a series of sharp peaks exist for the measurement results due to the self-homodyne demodulation. The phase noise at the sharp peaks are not accurate, which limits the usable offset frequency range. The larger the time delay, the lower the usable offset frequency range. To achieve a wide offset frequency range, the PLL technique is a good candidate. In a PLL based phase noise analyzer, the reference is a critical component, which should have the features of electronically-controlled tunability, low phase noise and low spurs [1]. Thanks to the development of photonic microwave generation, the photonic techniques are promising ways to get a high quality microwave signal due to their low phase noise, wideband tunability and potential of chip-scale packaging integration [13–23]. Among various photonic approaches, the optoelectronic oscillator (OEO) has been demonstrated to generate wideband tunable [20], ultra-low phase noise (−163 dBc/Hz at 6 kHz offset [18]) microwave or millimeter-wave signal. By using the OEO as the reference, it has great potential to improve the sensitivity of the phase noise analyzer without cross-correlation. In [24], a microwave phase noise measurement system by using an OEO is realized. The OEO serves as the LO of a down-conversion system. However, it requires an additional wideband, high sensitivity phase noise analyzer operated at low frequency.

In this paper, a novel microwave phase noise analyzer by using a photonic-based reference is proposed and experimentally demonstrated. In our scheme, the phase noise of the SUT is extracted by a PLL. The reference of the PLL is formed by the combination of an OEO and a direct digital synthesizer (DDS). Thanks to this low phase noise reference, we attain a phase noise analyzer with sensitivities of −114 dBc/Hz at 1 kHz offset and −139 dBc/Hz at 10 kHz offset without cross-correlation. By tuning the frequency control word of the DDS, the measurement frequency range is from 9 GHz to 11 GHz. The phase noise of three commercial microwave signal generators are successfully characterized by our proposed system. The measurement results agree well with those of the commercial phase noise analyzers.

The remaining paper is organized as follows. In Section 2, the system architecture and operation principle of our proposed phase noise analyzer are presented. After that, based on the proposed scheme, experimental results are shown in Section 3. Finally, a conclusion is drawn in Section 4.

2. System architecture and operation principle

In the following sub-sections, we will firstly show the system architecture of our proposed phase noise analyzer. After that, the operation principle of the frequency tunable reference will be given. Finally, we will present the theoretical analysis of the phase locking process and phase noise sensitivity of the system.

2.1 System architecture

The system architecture of the proposed phase noise analyzer is shown in Fig. 1. It is based on the PLL method. The key device is the reference, which is formed by the combination of an OEO and a DDS. It has a voltage-controlled input port, a coarse frequency tuning input port, and a microwave signal output port. The output frequency of the reference can be continuously tuned by changing the applied voltage on the voltage-controlled input port. Besides, by programming the frequency control word of the DDS, the frequency of the reference can be coarsely tuned in a wide frequency range. The phase of the SUT and the reference are compared by a phase detector. Here, we use a double-balanced mixer (DBM) as the phase detector. The phase detector converts the phase difference between the SUT and the reference to an error voltage. This error voltage is fed back to control the frequency of the reference after passing through a low noise amplifier (LNA) and a loop filter. By tuning the frequency of the reference via the DDS, the frequency of the SUT will fall inside the pull-in range of the PLL. After phase locked, the frequency of the SUT is exactly equal to that of the reference. Besides, the phase of them can be kept in quadrature. In this configuration, when the phase noise of the reference is much lower than that of the SUT, then the phase fluctuation of the SUT will be extracted at the output of the phase detector. The power spectral density (PSD) of the phase fluctuation of SUT is gotten by a Fast Fourier Transform (FFT) analyzer. Next, we will show the mathematical analysis of the operation principle in the following part.

 figure: Fig. 1

Fig. 1 System architecture of the proposed microwave phase noise analyzer. SUT: signal under test. LNA: low noise amplifier. DDS: direct digital synthesizer. FFT: fast Fourier transform.

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By neglecting amplitude noise, the outputs of the reference and SUT can be described as

Vr(t)=Arsin(ωrt+φr+Δφr(t)),
and
Vsut(t)=Asutsin(ωsutt+φsut+Δφsut(t)),
where Ar and Asut are the amplitude of the reference and SUT, ωr and ωsut are the angular frequencies of the reference and SUT, φr and φsut are the initial phase of the reference and SUT, Δφr(t) and Δφsut(t) are the phase fluctuations of the reference and SUT. If the reference and SUT serve as the two inputs of the DBM, the output voltage of the DBM is
Ud(t)=αVr(t)Vsut(t),
where α is the conversion loss of the DBM. By substituting Eqs. (1) and (2) into Eq. (3), and neglecting the sum frequency component, we can get the output of the DBM as
Ud(t)=12αArAsut{cos[φdiff(t)+Δφsut(t)Δφr(t)]},
where φdiff(t)=(ωsutωr)t+φsutφr is the phase difference between the SUT and reference. When the phase of the SUT and the reference are kept in quadrature, the condition of φdiff(t)=π2 will be satisfied. In this case, the output voltage of the DBM is

Ud(t)12αArAsutsin[Δφsut(t)Δφr(t)]

Note that the phase fluctuations of the reference and SUT are quite small. Besides, when the phase fluctuation of the reference is much lower than that of the SUT, we will have the condition of Δφr(t)<<Δφsut(t)<<1. In this case, Eq. (5) can be simplified as

Ud(t)KpdΔφsut(t),
where Kpd=12αArAsut is the voltage gain coefficient of the DBM. From Eq. (6), we can obtain the phase noise of the SUT at the output of the DBM.

2.2 Operation principle of the frequency tunable reference

The reference is a critical component for a PLL based phase noise analyzer. Low phase noise, low spurs, wideband tunability and voltage-controlled frequency tunability are demanded. Figure 2 shows the schematic diagram of the proposed reference. It is composed of two parts. The first is the dual-loop OEO, the other part is the frequency tuning system based on a DDS. To achieve the single oscillation mode of the OEO, we use a dual-loop structure [25,26]. In this configuration, there are two mechanisms to select the mode of the OEO, which are the bandpass filtering of the RF filter and Vernier effect of the oscillation modes of the dual-loop, as shown in Fig. 3. The final oscillation mode of the OEO is determined by the combination of these two mechanisms. By particularly choosing the fiber length of the single mode fiber (SMF2) used in the short loop, only one mode of the short loop can be selected by the electrical bandpass filter. Besides, the oscillation signals in the short and long loops must add up in phase for the sustained oscillation, only modes that coincide in frequency in each loop survive. It results in a single oscillation mode of the OEO. To achieve the continuous frequency tunability of the final oscillation mode, a voltage-controlled RF phase shifter (VCP) is utilized in the long loop of the OEO. The continuous frequency tuning range is limited to the mode spacing of the long loop [26]. To enlarge the frequency tuning range, we use a frequency tuning system via a DDS. The outputs of the OEO and the DDS are mixed through a RF mixer. Two tones can be generated, as shown by the schematic diagram of the electrical spectrum in Fig. 2. By changing the frequency control word of the DDS, the frequency of the two tones can be agilely tuned in a wide frequency range. Either one tone can be used as the reference. To reduce the contribution of the phase noise of the DDS to the reference, we use the frequency division of the OEO as the sampling clock of the DDS. In order to investigate the characteristics of the frequency tuning of the reference, we will present the theoretical analysis of the frequency tunability of the reference in the following part.

 figure: Fig. 2

Fig. 2 Schematic diagram of the frequency tunable reference. CW: continuous-wave. DOMZM: dual-output Mach-Zehnder intensity modulator. SMF1, and SMF2: single mode fibers. PD1, and PD2: photodiodes. VCP: voltage-controlled RF phase shifter. EC1, EC2, and EC3: electrical couplers. LPA: low phase noise amplifier. EBPF: electrical bandpass filter. DDS: direct digital synthesizer. foeo and fdds are the frequencies of the OEO and the DDS.

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 figure: Fig. 3

Fig. 3 Schematic diagram of the mechanisms of single mode selection in the dual-loop OEO. Δfs and Δfl are the mode spacings of the short and long loops. M is an integer number.

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The RF phase shift of the VCP can be changed by a control voltage. By assuming the phase shift is a linear function of the control voltage, it can be described as

Δφ=KpUc,
where Kp is the phase sensitivity of the VCP, Uc is the control voltage of the VCP. Due to the introduction of the RF phase shift, a time delay for the long loop of the OEO is induced. It can be described as
Δτ=Δφ2πf0,
where f0 is the frequency of the free-running OEO. The variation of the time delay for the long loop leads to the frequency changing of the oscillation signal. The ratio between the frequency variation and the frequency of the free-running OEO can be expressed as [27]
Δff0=Δττd,
where τd is the time delay of the long loop of the OEO. When the control voltage is applied to the VCP, the frequency of the OEO can be represented as

foeo=f0+Δf

By substituting Eqs. (7) - (9) into Eq. (10), the output frequency of the OEO can be derived as

foeo=f0+KpUc2πτd

From Eq. (11), the frequency of the OEO can be continuously tuned by the control voltage of the VCP. If the phase shift of the VCP is changed by 2π, the frequency variation of the OEO is 1/τd, which is equal to the mode spacing of the long loop. To enlarge the frequency tuning range, a DDS is utilized. The frequency of the output of the DDS is

fdds=N2mfclk,
where m is the number of bits of the phase accumulator of the DDS, N is the frequency control word of the DDS, fclk is the sampling clock of the DDS. Here, we use the frequency division of the OEO as the sampling clock of the DDS, it can be expressed as
fclk=1nfoeo,
where n is the frequency dividing ratio of the microwave frequency divider (MFD). By mixing the outputs of the DDS and the OEO through a DBM, two tones can be obtained at the output of the DBM. The frequencies of the two tones are

fr=foeo±fdds

By combining Eqs. (11) - (14), the frequencies of the two tones can be derived as

fr=f0+(1±1nN2m)Kp2πτdUc±1nN2mf0

The frequency sensitivity of the two tones can be defined as

Kv=(1±1nN2m)Kp2πτd

Note that the unit of the frequency sensitivity is Hz/V. From Eq. (15), the frequency of the two tones can be continuously tuned by changing the control voltage of VCP and widely tuned by programming the frequency control word of the DDS. The longer the time delay of the long loop, the lower the frequency sensitivity. According to the Nyquist sampling theorem, the maximum frequency of the DDS is half of the sampling clock. Consequently, the maximum frequency tuning range for either of the two tones is equal to the frequency of the half of the sampling clock of the DDS. Besides, the tuning resolution is determined by the number of bits of the phase accumulator and the sampling clock of the DDS.

2.3 Phase locking process

In order to investigate the dynamic properties of the phase locking for the phase noise measurement, we will theoretically analyze the evolution of the phase difference between the reference and SUT. Figure 4 shows the block diagram of the phase model of the PLL used in the phase noise analyzer in the time domain. Note that the phase fluctuations are not considered for the analysis of phase locking.

 figure: Fig. 4

Fig. 4 Block diagram of the phase model of the PLL used in the proposed phase noise analyzer.

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From Eq. (4), by neglecting the phase fluctuations of the SUT and reference, the output voltage of the phase detector can be expressed as

Ud(t)=Kpdcos(φdiff(t))

Since the loop filter is a linear time invariant (LTI) system, for the analysis in time domain, the transfer operator can be used to characterize the relationship between the input and output of the loop filter [28]. The feedback control voltage for the reference is

Uc(t)=F(p)[GUd(t)],
where G is the voltage gain of the LNA, F(p) is the transfer operator of the loop filter, p=ddt is the differential operator. Here, we use a second-order proportionally-integrating (PI) filter as the loop filter. Its transfer operator is [28,29]
F(p)=1+τ2pτ1p,
where τ1 and τ2 are the time constants of the loop filter. By applying the feedback control voltage to the voltage-controlled input of the reference, the phase of the reference can be expressed as

φr(t)=ωrt+φr+0t2πKvUc(t')dt'

Meanwhile, the phase of the SUT is

φsut(t)=ωsutt+φsut

The phase difference between the SUT and the reference is

φdiff(t)=φsut(t)φr(t)

By combining Eqs. (17) - (22), we can obtain the nonlinear differential equation of the phase difference as

τ1d2φdiff(t)dt22πKvKpdGτ2sin(φdiff(t))dφdiff(t)dt+2πKvKpdGcos(φdiff(t))=0

When the SUT is phase locked with the reference, the phase difference will be a constant value. In this case, the following conditions can be satisfied [29].

d2φdiff(t)dt2=dφdiff(t)dt=0

By combining Eqs. (23) and (24), the solutions of the phase difference after phase locked are

φdiff(t)=kπ±π2(k=0,±1,±2...)

From the results of Eq. (25), the phase of the SUT and reference can be kept in quadrature after phase locked. To study the dynamic properties of the phase locking, we present a numerical simulation of the evolution of the phase difference by using the model in Eq. (23). Table 1 lists the parameters used in the simulation.

Tables Icon

Table 1. Simulation parameters for the dynamics of the PLL

Figure 5 shows the simulation results of the evolution of the phase difference. Two cases are considered. The first case has a fixed frequency difference of 3.2 kHz and a variant initial phase difference between the SUT and reference, as shown in Fig. 5(a). For the second case, the initial phase difference is set to be π/3 and the frequency difference changes from −3.2 kHz to 3.2 kHz, as shown in Fig. 5(b). In the beginning, the phase difference varies over time. After a period of time, it converges to a constant value. The phase difference is integer multiples of π/2, which illustrates that the phase of the SUT and reference are kept in quadrature. Besides, the phase locking time is around milliseconds level.

 figure: Fig. 5

Fig. 5 Simulation results of the evolution of the phase difference. (a) With a frequency difference of 3.2 kHz and a variant initial phase difference. (b) With an initial phase difference of π/3 and a variant frequency difference.

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2.4 Phase noise sensitivity of the system

Phase noise sensitivity is one of the most important metrics to evaluate the performance of a phase noise analyzer. Here, we will theoretically analyze the sensitivity of our proposed system. A linear model (Laplace transform) can be used to characterize the phase noise of the PLL used in our system [30]. Figure 6 shows the block diagram of the phase noise model.

 figure: Fig. 6

Fig. 6 Block diagram of the phase noise model of the system. Δφsut(s), Δφr(s) and Δφout(s)are the phase fluctuations of the SUT, the reference and the output of the PLL. Δφdiff(s) is the phase difference at the output of the phase detector.

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From Fig. 6, the open-loop transfer function of the PLL can be expressed as

Hf(s)=KpdGF(s)Hr(s),
where F(s) is the transfer function of the loop filter, Hr(s) is the transfer function of the reference. They can be described as
F(s)=1+τ2sτ1s,
and

Hr(s)=2πKvs

According to the Mason’s Rule, the phase fluctuations of the output can be written as

Δφout(s)=Hf(s)1+Hf(s)Δφsut(s)+Hf(s)[1+Hf(s)]Kpd[npd(s)+nlf(s)]+11+Hf(s)Δφr(s),
where npd(s) and nlf(s) are the noise of the phase detector and loop filter. The phase fluctuations of at the output of the phase detector is

Δφdiff(s)=Δφsut(s)Δφout(s)

By combining Eqs. (29) and (30), the phase fluctuation at the output of the phase detector is

Δφdiff(s)=11+Hf(s)Δφsut(s)Hf(s)[1+Hf(s)]Kpd[npd(s)+nlf(s)]11+Hf(s)Δφr(s)

Note that the phase noise of the SUT, the reference, and the voltage noise of the phase detector and loop filter are independent. In order to get the PSD of the phase fluctuation, we take square modulus and substitute s=j2πf into Eq. (31). The PSD of the phase noise at the output of the phase detector can be written as

SΔφdiff(f)=|11+Hf(f)|2[SΔφsut(f)+SΔφr(f)]+|Hf(s)[1+Hf(s)]Kpd|2[Snpd(f)+Snlf(f)],
where f is the Fourier offset frequency from the carrier, SΔφsut(f) and SΔφr(f) are the PSD of the phase noise of the SUT and the reference, Snpd(f) and Snlf(f) are the PSD of the amplitude noise of the phase detector and the loop filter. From Eq. (32), the output of the phase detector includes the phase noise of the SUT, the noise of the reference, the phase detector and the loop filter. We can divide it into two parts. The first part includes the phase noise of the SUT, which is

SSUT(f)=|11+Hf(f)|2SΔφsut(f)

The second part is composed of the other noise sources, which represents the phase noise floor of the system. It is written as

Sfloor(f)=|11+Hf(f)|2SΔφr(f)+|Hf(f)[1+Hf(f)]Kpd|2[Snpd(f)+Snlf(f)]+SFFT(f)

Note that SFFT(f) is the PSD of the phase noise floor of the FFT analyzer. In Eq. (33), the term of |1/[1+Hf(f)]|2 is the phase noise transfer function of the SUT, which is induced by the PLL [29]. We plot it by using the parameters in Table 1, as shown in Fig. 7. The offset frequency range is from 10 Hz to 10 MHz. It shows a high-pass filtering characteristic of the phase noise transfer function. The sensitivity of the phase noise measurement will be suppressed at the low offset frequency, which limits the lowest offset frequency for the measurement in our system. When the gain of the feedback loop of the PLL is reduced, the cutoff frequency will be decreased. In order to guarantee an accurate phase noise measurement of the SUT, the cutoff frequency should be lower than the lowest offset frequency of interest. Beyond cutoff frequency, the sensitivity is determined by the noise of the reference, the phase detector, the loop filter, and the FFT analyzer, as shown in Eq. (34).

 figure: Fig. 7

Fig. 7 Phase noise transfer function of the SUT with a variant gain of the LNA used in the PLL.

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3. Experimental results and discussion

In order to verify our scheme, experiments based on the setup shown in Figs. 1 and 2 are performed. A continuous wave (CW) laser is used as the light source of the OEO. It has a fixed wavelength of 1550.12 nm, linewidth less than 5 kHz, and output power of 80 mW. A dual-output Mach-Zehnder intensity modulator (DOMZM, Eospace Inc.) with bandwidth of 40 GHz is utilized to realize electro-optical conversion. Two single-mode fibers (SMF1 and SMF2) with length of 2 km and 0.1 km are used to form a dual-loop OEO. Two photodiodes (PD1 and PD2, APIC Inc.) with the responsivity of 0.95 A/W, the saturation power of 50 mW, the 3-dB bandwidth of 20 GHz are used to convert the optical signals to electrical signals. Three low phase noise amplifiers (LPAs, Analog Devices Inc., HMC-C072) with the operation frequency range from 6 GHz to 12 GHz, the gain of 15 dB, the noise figure of 7 dB, and the saturation power of 17 dBm are cascaded to provide sufficient RF gain for the OEO. An electrical bandpass filter (EBPF) with the center frequency of 10 GHz and 3-dB bandwidth of 3 MHz is used to select the oscillation mode of the OEO. A VCP (CONNPHY Inc., CVPS-6G15G-360) with the RF phase tuning range larger than 360 degrees, the operation frequency range from 6 GHz to 15 GHz, and the control voltage range from 0 V to 5 V is used to realize the voltage-controlled frequency tunability of the OEO. An MFD (Analog Devices Inc., HMC862A) with a bandwidth of 20 GHz, the dividing ratio of 4 is used to frequency divide the 10 GHz OEO to a 2.5 GHz clock for the DDS. A DDS (Analog Devices Inc., AD9914) with the sampling clock up to 3.5 GHz, and frequency resolution of 190 pHz is used to realize the frequency tuning system. The residual phase noise of DDS are below −130 dBc/Hz at 1 kHz offset and −140 dBc/Hz at 10 kHz offset. An X-band DBM (Analog Devices Inc., HMC-C049) is used to perform the analog mixing of the OEO and DDS. The phase-detector is formed by a DBM (Analog Devices Inc., HMC-C049). A home-made second-order PI filter is used as the loop filter in the PLL. The home-made loop filter includes two parts, one is the bias circuit, the other is the second-order PI filter. The bias circuit is used to adjust the offset voltage of the feedback control signal for VCP. The PI filter is realized by only one operational amplifier.

3.1 Frequency tunability, stability and phase noise of the reference

Figure 8(a) shows the electrical spectra of the reference. A 10 GHz OEO and a DDS serve as the inputs of the mixer. Two tones are observed at the output of the mixer. By changing the frequency of the DDS from 100 MHz to 1 GHz with a step of 100 MHz, the frequency of the two tones can be tuned in a wide frequency range. The tuning range for the lower tone is from 9 GHz to 10 GHz. While for the upper tone, the tuning range is from 10 GHz to 11 GHz. Either of the two tones can be used as the reference of the PLL. To investigate the spurs of the reference, we measured the electrical spectrum of one tone with resolution bandwidth (RBW) of 1 Hz and observation span of 1 MHz, as shown in Fig. 8(b). The frequency is around 10.1 GHz. This tone has highly spectral purity. The side-mode suppression ratio (SMSR) is calculated to be higher than 100 dB. We also evaluate the transient response of the frequency switching of the reference, as shown in Fig. 8(c). The initial frequency of the reference is set to about 10.337 GHz. By changing the frequency control word of the DDS, the frequency of the reference is switched to around 10.347 GHz. The frequency switching time is estimated to be 176 ns. It exhibits a high-speed tunability of the reference. Figure 8(d) shows the voltage-controlled frequency characteristics of the reference. The control voltage of the VCP is changed from 0 V to 5 V. The frequency is quasi-linearly increased, as shown by the blue curve. The continuous frequency tuning range is around 200 kHz, which is adequate for phase locking. The largest pull-in range of the PLL is limited by the continuous frequency tuning range of the reference. Correspondingly, the frequency sensitivity is about tens of kHz/V, as shown by the red curve. This parameter can be theoretically estimated by Eq. (16). The time delay for the long loop (2 km) is about 10 microseconds. The phase sensitivity of the VCP is about 0.67π rad/V. The frequency sensitivity is calculated to be around 33.5 kHz/V. The experimental result is consistent in magnitude with the calculation.

 figure: Fig. 8

Fig. 8 (a) Tunable electrical spectra of the reference. (b) Electrical spectrum of the 10.1 GHz. (c) Transient response of frequency switching. (d) The frequency and frequency sensitivity of the reference versus the control voltage of the VCP.

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To investigate the phase noise performance of the generated microwave signal at the output of the mixer, we measured the single-sideband (SSB) phase noise of the OEO, the clock of DDS, the output of DDS and the output of mixer by using a high sensitivity phase noise analyzer (Rohde & Schwarz, FSWP26) via cross-correlation, which are illustrated in Fig. 9(a). The black curve presents the phase noise of the OEO. It shows phase noise of −114 dBc/Hz at 1 kHz offset and −140 dBc/Hz at 10 kHz offset for the 10 GHz carrier. There are some spurs at integer multiples of 100 kHz, which are the side-modes of the OEO. Note that the highest spur is below −128 dBc. Thanks to the frequency division of the OEO is used as the sampling clock of the DDS, it guarantees a high spectral purity of the output 100 MHz signal of the DDS, as shown by the blue curve. As a consequence, by analog mixing the outputs of OEO and DDS, it indicates an extremely low phase noise of the generated 10.1 GHz signal, as shown by the magenta curve. The frequency stability of the generated 10.1 GHz signal can be characterized in the time domain by Allan deviation, as shown in Fig. 9(b). The averaging time is from 100 μs to 10 s. At the 1-second average, the Allan deviation is on the order of 10−8.

 figure: Fig. 9

Fig. 9 (a) SSB phase noise of the 10 GHz OEO, 2.5 GHz sampling clock of the DDS, 100 MHz output of the DDS, and 10.1 GHz output of the reference. (b) Allan deviation of the 10.1 GHz reference.

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3.2 Phase locking process of the system

The dynamic properties of the phase locking for the extraction of phase noise are measured. Figures 10(a) and 10(b) show the transient responses of the frequency and phase of the reference. The frequency difference between the SUT and reference is around 3.3 kHz, which is lower than the pull-in range of the PLL. In this case, the PLL will acquire locking. During the phase locking process, the frequency of the reference switches to another frequency after a damping oscillation. The phase locking time is around 2 milliseconds, which coincided with the theoretical predictions shown in Fig. 5. Besides, an abrupt phase variation occurs during the phase locking process, which is shown in Fig. 10(b). After phase locked, the frequency of the reference is same as that of the SUT. Figure 10(c) shows the measured voltage of the output of the phase detector, which is close to zero Volt. It results from the quadrature phase relationship between the SUT and reference after phase locked, as shown in Eq. (25) and Fig. 5. In order to calibrate the phase noise measurement system, we need to measure the phase sensitivity of the phase detector. It is accomplished by using two signal sources with a small frequency difference as the inputs of the phase detector. In our experiment, we set the frequency difference as 1 MHz. The frequencies of the two input signals for the phase detector are 10.1 GHz and 10.101 GHz. The power of the reference and SUT are set to 10 dBm and 0 dBm, respectively. It results in a beat-note at the output of the phase detector. Figure. 10(d) shows the waveform of the beat-note in time domain. Theoretically, the phase sensitivity is equal to the half of the peak-to-peak voltage of the beat-note, which is 0.23 V/rad in this case. In order to ensure the accuracy of the phase noise result, it suggests that the phase sensitivity should be measured before each phase noise measurement.

 figure: Fig. 10

Fig. 10 (a), and (b) Transient responses of frequency and phase during the phase locking process. (c) The output of phase detector after phase locked in time domain. (d) The 1 MHz beat-note between reference and SUT in time domain.

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3.3 Phase noise sensitivity of the system

The phase noise sensitivity of the proposed system is evaluated, as shown in Fig. 11. In our experiment, we set the time constants (τ1 and τ2) of the second-order PI filter shown in Eq. (19) to be 20 ms and 0.1 ms, respectively. It makes the cutoff frequency of the phase noise transfer function shown in Fig. 7 lower than 100 Hz, which ensures the usable lowest offset frequency is 100 Hz. The blue, red, and olive curves are the background noise, the phase noise floor of FFT analyzer, and the phase noise of the reference, respectively. The background noise is contributed by the noise of the mixer, LNA, and the loop filter. To measure the background noise, the SUT is disconnected. The PSD of the amplitude noise of the output of loop filter is measured by the FFT. The background noise is achieved by calibrating the PSD of this amplitude noise to phase noise via the phase sensitivity of the phase detector. There are some spurs for the background noise, which are induced by the interference of the power supply. Furthermore, there are some spurious at integer multiples of 100 kHz for the phase noise of the reference. It is caused by the side-modes of the OEO. From Eq. (34), the phase noise sensitivity of the proposed phase noise analyzer is determined by the sum of the three noise sources, as shown by the magenta curve. It indicates that the sensitivities are −114 dBc/Hz at 1 kHz offset and −139 dBc/Hz at 10 kHz offset without cross-correlation. Note that the phase noise sensitivity at offset frequency range from 100 Hz to 1 kHz is limited by the phase noise of the reference. The near-carrier phase noise of the reference is influenced by the temperature fluctuations, vibrations, Rayleigh scattering and Brillouin scattering in the fiber [31]. By frequency modulating the laser, and placing the fiber in a temperature-controlled and vibration isolation environment, the sensitivity of the system can be improved at near-carrier offset.

 figure: Fig. 11

Fig. 11 Background noise, phase noise floor of the FFT analyzer, phase noise of the reference, and phase noise floor of the system.

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3.4 Phase noise measurement of microwave signal generators

To verify the proposed phase noise analyzer, the phase noise of three microwave signal generators (Keysight E8257D, Anritsu MG3695A, and Keysight N5247A) are tested via our scheme, as shown in Figs. 12(a) - 12(c). Besides, we make a comparison between the results measured by our system and that of two commercial phase noise analyzers (Keysight E5052B + E5053A, and Rohde & Schwarz FSWP26). The offset frequency range is from 100 Hz to 10 MHz. With offset frequency below 1 MHz, our measured results agree well with those of the commercial phase noise analyzers. The measurement errors above 1 MHz offset in Figs. 12(a) and (b) are induced by the noise floor of the FFT analyzer. Besides, there are some spurious for the results of our system. It is induced by the spurs of the reference and the phase-locked circuit. In order to investigate the wideband property of our system, the phase noise of the SUT (Anritsu MG3695A) with different frequencies are measured. The frequency of the SUT is changed from 9 GHz to 11 GHz with a step of 100 MHz. We make a comparison of the phase noise at 10 kHz offset measured by our system and the commercial phase noise analyzer, as shown in Fig. 12(d). The difference between them are all below 2 dB, which indicates that a good measurement accuracy can be achieved by our system.

 figure: Fig. 12

Fig. 12 (a), (b), and (c) SSB phase noise measurement of three microwave signal generators by our proposed system and two commercial phase noise analyzers. (d) A comparison of the measured SSB phase noise at 10 kHz offset by our system and the commercial phase noise analyzer (Keysight, E5052B + E5053A) with different frequencies.

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4. Summary

In summary, a high sensitivity PLL-based microwave phase noise analyzer by using a photonic-based reference has been proposed and experimentally demonstrated. The reference is formed by the analog mixing of the outputs of an OEO and a DDS. The OEO is a promising way to overcome the limitation of the phase noise of pure electronic references at high frequency, which can bring the sensitivity of the phase noise analyzer to a new level at high-frequency carrier. By using the proposed low phase noise reference, we attain a phase noise analyzer with an excellent sensitivity without cross-correlation at X-band. This scheme is suitable for the phase noise characterization of the high-frequency, and low phase noise microwave oscillators with wide Fourier offset frequency range. As the OEO’s phase noise independent of oscillation frequency, it is promising to extend the operation frequency of the proposed phase noise analyzer to the millimeter-wave range while maintaining high sensitivity.

Funding

National Natural Science Foundation of China (Grant No. 61690194, Grant No. 61805003), China Postdoctoral Science Foundation (Grant No. 2018M630035).

Acknowledgments

The authors would like to thank Rohde & Schwarz for offering the phase noise analyzer (FSWP26).

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Figures (12)

Fig. 1
Fig. 1 System architecture of the proposed microwave phase noise analyzer. SUT: signal under test. LNA: low noise amplifier. DDS: direct digital synthesizer. FFT: fast Fourier transform.
Fig. 2
Fig. 2 Schematic diagram of the frequency tunable reference. CW: continuous-wave. DOMZM: dual-output Mach-Zehnder intensity modulator. SMF1, and SMF2: single mode fibers. PD1, and PD2: photodiodes. VCP: voltage-controlled RF phase shifter. EC1, EC2, and EC3: electrical couplers. LPA: low phase noise amplifier. EBPF: electrical bandpass filter. DDS: direct digital synthesizer. f oeo and f dds are the frequencies of the OEO and the DDS.
Fig. 3
Fig. 3 Schematic diagram of the mechanisms of single mode selection in the dual-loop OEO. Δ f s and Δ f l are the mode spacings of the short and long loops. M is an integer number.
Fig. 4
Fig. 4 Block diagram of the phase model of the PLL used in the proposed phase noise analyzer.
Fig. 5
Fig. 5 Simulation results of the evolution of the phase difference. (a) With a frequency difference of 3.2 kHz and a variant initial phase difference. (b) With an initial phase difference of π/3 and a variant frequency difference.
Fig. 6
Fig. 6 Block diagram of the phase noise model of the system. Δ φ sut (s), Δ φ r (s) and Δ φ out (s)are the phase fluctuations of the SUT, the reference and the output of the PLL. Δ φ diff (s) is the phase difference at the output of the phase detector.
Fig. 7
Fig. 7 Phase noise transfer function of the SUT with a variant gain of the LNA used in the PLL.
Fig. 8
Fig. 8 (a) Tunable electrical spectra of the reference. (b) Electrical spectrum of the 10.1 GHz. (c) Transient response of frequency switching. (d) The frequency and frequency sensitivity of the reference versus the control voltage of the VCP.
Fig. 9
Fig. 9 (a) SSB phase noise of the 10 GHz OEO, 2.5 GHz sampling clock of the DDS, 100 MHz output of the DDS, and 10.1 GHz output of the reference. (b) Allan deviation of the 10.1 GHz reference.
Fig. 10
Fig. 10 (a), and (b) Transient responses of frequency and phase during the phase locking process. (c) The output of phase detector after phase locked in time domain. (d) The 1 MHz beat-note between reference and SUT in time domain.
Fig. 11
Fig. 11 Background noise, phase noise floor of the FFT analyzer, phase noise of the reference, and phase noise floor of the system.
Fig. 12
Fig. 12 (a), (b), and (c) SSB phase noise measurement of three microwave signal generators by our proposed system and two commercial phase noise analyzers. (d) A comparison of the measured SSB phase noise at 10 kHz offset by our system and the commercial phase noise analyzer (Keysight, E5052B + E5053A) with different frequencies.

Tables (1)

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Table 1 Simulation parameters for the dynamics of the PLL

Equations (34)

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V r (t)= A r sin( ω r t+ φ r +Δ φ r (t)),
V sut (t)= A sut sin( ω sut t+ φ sut +Δ φ sut (t)),
U d (t)=α V r (t) V sut (t),
U d (t)= 1 2 α A r A sut {cos[ φ diff (t)+Δ φ sut (t)Δ φ r (t)]},
U d (t) 1 2 α A r A sut sin[Δ φ sut (t)Δ φ r (t)]
U d (t) K pd Δ φ sut (t),
Δφ= K p U c ,
Δτ= Δφ 2π f 0 ,
Δf f 0 = Δτ τ d ,
f oeo = f 0 +Δf
f oeo = f 0 + K p U c 2π τ d
f dds = N 2 m f clk ,
f clk = 1 n f oeo ,
f r = f oeo ± f dds
f r = f 0 +(1± 1 n N 2 m ) K p 2π τ d U c ± 1 n N 2 m f 0
K v =(1± 1 n N 2 m ) K p 2π τ d
U d (t)= K pd cos( φ diff (t))
U c (t)=F(p)[G U d (t)],
F(p)= 1+ τ 2 p τ 1 p ,
φ r (t)= ω r t+ φ r + 0 t 2π K v U c ( t ' )d t '
φ sut (t)= ω sut t+ φ sut
φ diff (t)= φ sut (t) φ r (t)
τ 1 d 2 φ diff (t) d t 2 2π K v K pd G τ 2 sin( φ diff (t)) d φ diff (t) dt +2π K v K pd Gcos( φ diff (t))=0
d 2 φ diff (t) d t 2 = d φ diff (t) dt =0
φ diff (t)=kπ± π 2 (k=0,±1,±2...)
H f (s)= K pd GF(s) H r (s),
F(s)= 1+ τ 2 s τ 1 s ,
H r (s)= 2π K v s
Δ φ out (s)= H f (s) 1+ H f (s) Δ φ sut (s)+ H f (s) [1+ H f (s)] K pd [ n pd (s)+ n lf (s)]+ 1 1+ H f (s) Δ φ r (s),
Δ φ diff (s)=Δ φ sut (s)Δ φ out (s)
Δ φ diff (s)= 1 1+ H f (s) Δ φ sut (s) H f (s) [1+ H f (s)] K pd [ n pd (s)+ n lf (s)] 1 1+ H f (s) Δ φ r (s)
S Δ φ diff (f)=| 1 1+ H f (f) | 2 [ S Δ φ sut (f)+ S Δ φ r (f)]+| H f (s) [1+ H f (s)] K pd | 2 [ S n pd (f)+ S n lf (f)],
S SUT (f)=| 1 1+ H f (f) | 2 S Δ φ sut (f)
S floor (f)=| 1 1+ H f (f) | 2 S Δ φ r (f)+| H f (f) [1+ H f (f)] K pd | 2 [ S n pd (f)+ S n lf (f)]+ S FFT (f)
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