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We demonstrate the first quantum dot (QD) laser on a silicon substrate with efficient coupling of light to a silicon waveguide under the QD gain region. Continuous wave operation up to 100 °C and multiwavelength operation are demonstrated, paving the way towards highly efficient CMOS-compatible, uncooled, WDM sources.
© 2016 Optical Society of America
1. Introduction
Photonic interconnects are becoming increasingly important in high-performance computers, large data centers, hyperscale computing, and cloud computing environments [1]. Currently, the cost and reliability of the light source limits silicon-based integrated photonics deployment in these fields to distances on the order of a kilometer or above. Robust on-chip laser operation in a temperature-varying environment with convenient low-loss light coupling to silicon photonic circuits is a vital step towards their ubiquitous adoption. In particular, the integration of quantum dot (QD) gain material on silicon has many intrinsic benefits over quantum well (QW) gain material.
Due to the three dimensional confinement of carriers, QD lasers promise higher temperature stability and lower threshold current densities when compared to quantum well lasers. These promises have been realized by the demonstration of QD lasers that operate at a stage temperature of 220 °C [2], have negligible threshold variation between −40 and 100 °C [3], and have threshold current densities as low as 19 A/cm2 [4]. In addition, due to the size distribution of the dots, QD lasers have a wide gain bandwidth [5], which allows for a larger channel count in a WDM link. Another advantage of the QD gain material is that it has a smaller surface recombination velocity and diffusion length when compared to QW gain material [6]. Consequently, the non-radiative recombination from dangling bonds (e.g., at etch-exposed active region) has a smaller contribution to the threshold current, and it is therefore possible to realize high efficiency lasers with narrower mesas when compared to QW gain material. These narrower mesas also make it easier to realize single mode operation which further improves the efficiency of the laser. It has also been found that QD lasers have a low relative intensity noise (RIN) [7]. Single-section QD-based Fabry-Perot lasers with a RIN low enough for error-free operation at 10 Gb/s have been demonstrated [8,9]. Finally, QD lasers have been shown to be less susceptible to feedback [10], which reduces the requirements for integrating isolators, thus reducing device complexity and costs.
The above advantages make QD lasers a particularly attractive candidate for a comb laser in datacom applications where the temperature varies between 30 and 85 °C. Before these devices can be deployed at a large scale, a commercially viable solution must be found. Using a pure III-V approach limits a foundry to using relatively small wafers ~150 mm in diameter at relatively large processing nodes of ~250 nm. The integration on silicon substrates, on the other hand, would potentially allow the use of widely available CMOS foundries which would result in high-volume, low-cost integrated III-V lasers with high-quality and reliable silicon photonics. Furthermore, the integration of the laser source directly on silicon would reduce coupling losses (improve the link budget) and packaging costs inherent in multi-chip solutions. The most promising integration scheme will take advantage of high performance active devices while it will also take advantage of the excellent optical properties of silicon (low optical losses). Typical integration schemes include growth [11,12], flip-chip bonding [13], and wafer bonding [14,15]. Numerous wafer-bonded approaches use a metal layer between the silicon and the GaAs wafers to facilitate bonding. This metal layer may increase optical losses if it overlaps with the lasing mode. These approaches also use an electrical contact on the silicon substrate, which requires a highly doped silicon layer. This further increases optical losses [16], and prevents the use of a buried oxide layer. Therefore, light cannot be confined in the silicon for waveguiding. So far, only one bonded approach has been demonstrated on an SOI wafer without an electrical contact on the silicon substrate; however, no coupling of the optical mode to the silicon waveguide was demonstrated [17].
A fundamental advantage of our approach over other wafer-bonded approaches is that similar to other hybrid silicon approaches [18], the bonding interface between the silicon and the III-V consists of a dielectric with low optical losses rather than a high-loss metal layer. Furthermore, both electrical contacts are formed on the III-V. This has two important consequences. First, it allows us to use undoped silicon as the waveguide layer, further reducing optical losses. Second, it allows us to use a buried oxide layer which prevents the optical mode from leaking into the silicon substrate. The above platform allows the seamless and low-loss integration of hybrid silicon quantum dot lasers (HSQDL) with high-quality silicon photonic components such as (de)multiplexers, grating couplers, and active components such as modulators and photodetectors.
2. Device design and fabrication
A cross-sectional diagram of our HSQDL is shown in Fig. 1(a). It consists of an SOI wafer with etched air trenches to form a silicon rib waveguide. A p-i-n GaAs-based diode laser structure with an InAs QD active region and 8 layers of QDs totaling 320 nm in thickness was then transferred to the SOI substrate using an O2 plasma-assisted direct bonding process [19]. The barriers between the QD layers are p-doped as this was shown to improve T0, the differential efficiency, and the differential gain [20]. A cross-sectional SEM image of a fabricated device where the tapers have been polished off is shown in Fig. 1(b).
Fig. 1 (a) Device cross-sectional diagram. (b) Scanning electron micrograph of a polished cross section. The tapers were polished off in oder to show the gain region. The air trench between the rib waveguide and the silicon cladding is filled with polishing residue. Fundamental mode calculation for (c) 1.8- and (d) 0.7-μm-wide silicon waveguide underneath a 6-μm-wide III-V mesa. (e) Schematic diagram of the taper design. Only the waveguiding layers are shown, while the metal layers have been omitted for clarity. For the devices under investigation, Lt1 = 120 μm, and Lt2 = 72 μm and the laser cavity is formed by polishing the passive silicon waveguide facets.
Using a fixed mesa width and etch depth, lasers with varying QD-confinement factors can be realized as the overlap of the optical mode with the QD region can be tuned by adjusting the width ‘w’ of the silicon waveguide. This is illustrated in Fig. 1(c), 1(d), where silicon waveguide widths of 1.8 and 0.7 μm yield QD confinement factors of 14% and 55%, respectively, with no change in the III-V mesa width or etch depth. This is an important aspect of the hybrid silicon approach – the optical mode can be transferred to and from the silicon waveguide using mode converters (tapers) in the silicon waveguide, thus relaxing the tolerance on the photolithographic alignment and resolution during the III-V mesa lithography and etch. The mode converter in the present device consists of two taper levels as illustrated in Fig. 1(e). By using a narrower Si waveguide, the light is mostly confined in the III-V section for maximal optical gain in most of the device cavity. As the light is exiting the gain region, it passes through the first level where the silicon waveguide width is tapered linearly from 0.7 μm to 2 μm over a length of 120 μm. After this taper level, the overlap of the optical mode with the silicon waveguide is ~90%. In the second taper level, the III-V width is tapered linearly from 6 μm to ~0.2 μm over a length of 72 μm. The length of the tapers were chosen to give ~90% mode conversion efficiency in each taper or over 80% for the whole taper. By employing constant loss tapers as described in [21], the tapers could perhaps be shortened without compromising efficiency. Leakage from the III-V mesa to the Si cladding is not possible as the air trenches prevent efficient coupling.
The SOI and GaAs QD material were purchased from SOITEC and QD Laser, Inc., respectively. Devices were fabricated on a 100 mm Silicon-on-Insulator (SOI) wafer with a top silicon thickness of 400 nm and a buried oxide thickness of 1000 nm. Rib waveguides were defined using 248-nm DUV lithography and etched to a depth of 320 nm. All following lithography steps were performed on a 365 nm i-line stepper. Vertical outgassing channels were defined to facilitate a high yield bond between the SOI and the GaAs wafer. Before bonding, the SOI wafer was cleaned in SC1 (DI:NH4OH:H2O2 = 5:1:1, 80 °C) and SC2 (DI:HCl:H2O2 = 5:1:1, 80 °C) solutions for 10 minutes each with a BHF dip after each solution followed by repeated ultrasonic cleaning in Isopropanol until the sample was free of particles. The GaAs wafer was cleaned in Acetone and Isopropanol until no particles remained on the sample surface. Just before bringing the samples into physical contact, both samples were exposed to a 30-second-long O2 plasma to form a native oxide. Once in contact, the bonded samples was annealed for ~14 hours at a temperature of 200 °C while applying a pressure of ~2 MPa on the bond. The GaAs substrate was then mechanically thinned to ~75 μm while the remainder was removed in a chemical solution of NH4OH:H2O2. The p-contact was defined by lifting off Ni/Pd/Au. GaAs mesas were formed in a dry etch using BCl3/Cl2/Ar. The etch depth was monitored using a 980 nm laser, and etching was stopped once it had reached the center of the 320-nm-thick active region. The remaining GaAs was removed in a wet chemistry consisting of Citric acid (1 Molar):H2O2 (30%) which has a high selectivity to the Al0.4Ga0.6As etch stop layer. The Al0.4Ga0.6As layer was etched in a solution of K2Cr2O7:H3PO4 which has a high selectivity to the n-GaAs contact layer in the lower cladding. The n-contact was formed by lifting off Pd/Ge/Au. The devices were passivated using 600-nm-thick SiO2, before vias were formed and probe pad metal was evaporated. The fabricated devices were diced into multiple laser bars and the facets were polished to form ~34% mirrors.
3. Device characterization
Lasers with a 6-μm-wide mesa and a 0.7-μm-wide silicon waveguide were tested. The laser bar was 3 mm long, and had a 2-mm-long gain region while the rest of the cavity was taken up by tapers and a passive silicon waveguide. Using an integrating sphere, continuous wave (CW) light-current (LI) data as a function of stage temperature were measured as shown in Fig. 2(a) and lasing is seen up to 100 °C. We measure output powers up to 12 mW at drive currents up to 200 mA, with no thermal roll-over being observed. Higher currents were not tried as the devices exhibited a high series resistance due to a fabrication error in the metallization step. The CW threshold current as a function of stage temperature is plotted in Fig. 2(b). The threshold current dependence on temperature is described by the relation [22]
where T0 is the characteristic temperature, and Ith is the threshold current of the device. For our device, we observe three distinct regions in the range of 20 to 100 °C. Between 20 and 40 °C, a very small increase in threshold current is observed. This yields a T0 of 333 K. Between 40 and 60 °C a moderate increase in the threshold corresponding to a T0 = 125 K is seen. Finally, between 60 and 100 °C, the device exhibits a T0 of 61 K. The high T0 at low temperatures is hypothesized to be from Auger recombination which is inversely proportional to temperature [23] and it is a direct result of the p-doping in the barriers between the QD layers [19]. The T0 of 125 K is comparable to the results from other groups [17], and about 30 K higher than QW-based InP lasers at 1.3 μm [24]. We anticipate improved performance with a lower device series resistance by using a better metallization process as this minimizes Joule heating. Further improvements are expected by incorporating thermal shunts [25, 26]. These shunts would connect the high temperature region (the p-metal for example) with the silicon substrate, circumventing the thermally insulating buried oxide layer of the SOI wafer.Fig. 2 (a) LI and (b) threshold current data as a function of stage temperature. Lasers were measured on a temperature controlled stage using a DC current source and an integrating sphere. The integrating sphere measured the light out of one facet.
Typical optical spectra below and above the threshold current from a device with an 8-μm-wide mesa with ΓQD = 55% at a stage temperature of 20 °C are shown in Fig. 3(a). These data were measured b coupling light out of the passive silicon waveguide using a lensed fiber wth a spot size of 2 μm. Below threshold, a broad spectrum is seen while above threshold a clear narrowing of the spectrum, consistent with lasing, is observed. Since the device includes no narrow wavelength selective filter, multiple longitudinal cavity modes lase simultaneously as shown in Fig. 3(b). This is the result of the large gain bandwidth of the QD material along with the small channel spacing of the cavity (0.08 nm, 14.3 GHz). The mode spacing is consistent with the laser cavity being formed by the polished silicon facets. This channel spacing is too small for them to be practical in a high speed (10 + GHz) WDM link since the modulation sideband of one channel would overlap with that of another channel. By reducing the cavity length to ~860 μm a mode spacing of 50 GHz can be achieved. This is large enough to avoid crosstalk between neighboring channels, while it is also small enough to allow a large number of channels [27]. The smaller cavity length can be realized by using integrated mirrors such as reflective multimode interferometers [28], distributed bragg reflectors, or a ring configuration, so it is possible to realize an integrated laser on Si without polishing facets. At temperatures up to 100 °C, lasing still occurs from the QD ground state, not from the excited state as shown in Fig. 3(c). Lasing from the excited stated is undesired as it would result in vastly different lasing dynamics. Near field images in Fig. 3(d), 3(e) show the polished silicon facet with the laser off and on, respectively, proving that the optical mode is coupled to the silicon waveguide.
Fig. 3 (a) Optical spectra below and above threshold. (b) Optical spectrum in linear scale at 114 mA. (c) Optical spectrum at 100 °C. No lasing from the excited state is observed. Near field image of the polished laser facet with the laser (d) turned off and (e) on.
Threshold current density data from devices with identical mesa widths (6 μm) but variable QD confinement factors are shown in Fig. 4(a). QD confinement factors of 14, 25, and 55% correspond to 1.8-, 1.3-, and 0.7-μm-wide silicon waveguides underneath the III-V mesa. The device with a QD confinement factor of ~55% has the lowest threshold current density as the optical mode has a higher overlap with the QD region resulting in more gain. The difference between data from Wafer 1 and Wafer 2 is likely due to variations in facet polishing uniformity and therefore mirror reflectivity. The threshold current density as a function of mesa width for a constant QD confinement factor of 14% is shown in Fig. 4(b). We see no significant increase as the mesa width is reduced indicating that sidewall recombination is negligible at these mesa widths. The scatter in the data is likely due to local polishing nonuniformity or the presence of higher order modes. These data suggest that it is feasible to realize mesas on the order of 2 μm in width without a significant increase of the threshold current due to sidewall non-radiative recombination. Narrower mesas will help in the suppression of higher order modes and avoid current spreading issue to favor higher efficiencies from those devices. It also allows a small bending loss for a microring-type device. However, too narrow mesas will also lead to an increase in the optical losses as the fundamental mode will have a larger overlap with the etched sidewall. The optimal mesa width depends on the specific waveguide design, which will be the subject of future studies.
Fig. 4 (a) Threshold current density as a function of QD confinement for identical lasers from two different dies. Lgain = 2 mm, Lcavity = 3 mm, wmesa = 6 μm. (b) Threshold current density as a function of mesa width. Lgain = 1.4 mm, Lcavity = 2 mm, ΓQD = 55%.
In transmission links that use amplitude modulation, the RIN of each individual comb line is the most important characteristic of the comb laser. In QW-based FP lasers, the RIN is typically limited by the competition of multiple longitudinal modes for optical gain – mode partition noise – and it was shown that this effect is less pronounced in QD lasers [6]. Unfortunately, the study in [6] only measured the RIN of the whole laser, not the RIN of individual comb lines. Further studies are required to see if the reduction in total laser RIN translates to a reduction in RIN of the individual comb lines. External optical feedback further contributes to RIN [29], and since QD lasers are more tolerant to feedback [9], a lower RIN can be expected. The RIN can be further reduce by placing an optical amplifier after the laser and driving the amplifier into saturation. This reduces RIN because of gain saturation inside the amplifier.
4. Conclusions
This paper demonstrates the first hybrid silicon QD laser with simple and low-loss coupling to the silicon waveguide. The QD material was integrated on the silicon in a way that takes advantage of the low loss properties of the silicon waveguide. It is therefore possible to integrate these lasers with other devices such as modulators, (de)multiplexers, and photodetectors. We demonstrated high temperature operation of up to 100 °C and threshold current densities as low as 271 A/cm2 despite significant self-heating due to a poor metallization process. We have also shown that for 4-μm-wide devices, the threshold current does not seem to be dominated by sidewall recombination current. It is therefore possible to realize narrower single mode devices with higher efficiencies. We expect improved device performance with better n-contacts, integrated mirrors, and thermal shunts. These devices are attractive candidates for uncooled operation in data centers.
Acknowledgments
The authors would like to thank Chong Zhang for dicing the samples, and Jared Hulme, Alan Liu, and Eric Stanton for helping with device measurements.
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