1. Introduction

As the field of silicon photonics matures, the focus of development efforts is changing. While substantial work is still dedicated to component design, focus is gradually shifting toward component integration. The push towards ever higher levels of integration has led to the establishment of standards in materials and fabrication methods. Over the past decade, silicon-on-insulator (SOI) with a 220 nm thickness device layer has emerged as the standard platform for photonic integrated circuits (PICs). Since properties of thin-film waveguides are highly dependent on physical dimensions, however, a thickness standard inherently implies a compromise between the benefits of standardization and application-specific optimal performance. For instance, PICs optimized for a 220 nm thick device layer cannot benefit from components optimized for the 130 nm SOI CMOS Freescale-Luxtera platform [1,2] that makes use of 300 nm thick SOI device layer. Indeed, optimal waveguide thickness varies greatly according to the application [3]. For example, according to [4], the optimal waveguide dimensions for high-Q low-loss ring resonators are 700 nm × 120 nm for TE polarization and 480 nm × 260 nm for TM polarization. In another example involving grating couplers, adding a 150 nm poly-silicon overlay on top of the 220 nm device layer reduces insertion losses [5]. Though achieving a heterogeneous range of device-specific lateral dimensions across a PIC poses no problem for advanced modern fabrication methods, locally fine-tuning waveguide vertical dimensions is more challenging. This paper describes a novel CMOS-compatible method for locally thinning Si photonic components to achieve device-specific optimal thickness.

There are two main challenges in “opening-up” the vertical dimension as a design parameter in integrated silicon photonics. First, control over thickness must be very precise (sometimes within ± 2 nm). This can be achieved with a slow etching or deposition process. Second, impedance-matching transitions between zones of different thickness are required to minimize insertion losses between devices. In general, this is harder to achieve. Indeed, most existing techniques used on semiconductors to create the long vertical slopes required for impedance-matching use non-standard or hard to control fabrication processes [6,7]. We have developed a method that meets both requirements yet uses standard microfabrication processes. The method is based on the thermal oxidation of silicon, a mature process where the silicon consumption during SiO₂ growth is highly predictable. Indeed, thermal oxidation is used in the fabrication of a variety of silicon photonics devices such as waveguides [8], mode converters [9], and oxidized SOI made from bulk silicon [10]. Moreover, local oxidation of silicon (LOCOS) gives rise to a phenomenon called “bird’s beak” [11] which effectively creates the required impedance-matching Si vertical slopes between zones of different thickness.

The following describes a modified LOCOS process to fabricate localized impedance-matching waveguide transitions between zones of different thickness. As a demonstration, we designed and fabricated a TE-pass filter, similar in structure to a proposed TM-pass filter that was simulated numerically by others [12]. The design and simulation process used to develop the filter are detailed below, followed by the fabrication process. Finally, characterization methods and experimental measurements of performance are presented.

2. Design of vertical tapers and TE-pass filter

Thermal oxidation is normally viewed as a way to grow SiO₂. Here, this method is used to consume silicon in a highly controllable manner. Indeed, when SiO₂ is grown, the oxide layer thickness increases by 54% above the original oxide surface and by 46% below, resulting in silicon consumption [13]. The oxidation time and desired oxidation thickness can be calculated precisely using online calculators [14,15] or by using the constants and equations in [16,17].

In the standard LOCOS process, oxygen diffusion under the Si₃N₄ layer forms a “bird beak” as shown in Fig. 1(a) [11]. This is generally considered a problem to be minimized. In our work, however, it is an asset used to create impedance-matching vertical tapers of the required length. The modified LOCOS process, shown in Fig. 1(b), was developed to take advantage of this effect whereby the thin SiO₂ layer under the Si₃N₄ film, often called pad oxide, is replaced with a thicker layer. As a result, Si oxidation will result in a longer transition region between the thinned and un-thinned regions.

 

Fig. 1 (a) Standard LOCOS process; (b) modified LOCOS process designed to increase transition length.

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For a given vertical Si consumption rate and pad oxide thickness, the transition length can be roughly estimated using the constants and equations found in [16,17]. For instance, wet thermal oxidation at 1200 °C for 5 hours and 49 minutes of a 5 µm thick pad will result in 210 nm of Si consumption vertically and a ~14 µm long taper. As stated above, this modified LOCOS process is totally CMOS-compatible.

To demonstrate the process in a real silicon photonics application, a TE-pass filter was fabricated based on a thinned waveguide between two vertical tapers (Fig. 2). The thinned region of the waveguide was designed with cross-section dimensions that only support the fundamental quasi-TE₀₀ mode. The filter was fabricated from a SOI substrate with a 260 nm thick device layer and all the optical circuits were buried in a SiO₂ matrix (cladding).

 

Fig. 2 3D schematic diagram of the TE-pass filter.

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To determine the optimal dimensions of the structure, Lumerical 3D finite-difference time-domain (FDTD) [18], Photon Design FIMMWAVE and FIMMPROP [19] simulations were performed. Lumerical simulations were used to find the thinned waveguide cross-section that could only support the fundamental quasi-TE₀₀ mode. According to the simulations, at refractive indices of 3.4734 for Si, 1.449 for the SiO₂ of the BOX and 1.459 for the SiO₂ of the cladding at 1550 nm (SiO₂ indices are based on ellipsometry measurements), the quasi-TE₀₀ is the only mode guided by a 1 µm × 50 nm waveguide. As shown in the Fig. 3, for the same 1 µm width, a waveguide with a height of 260 nm has 7 guided modes (quasi-TE₀₀, quasi-TE₁₀, quasi-TE₂₀, quasi-TM₀₀, quasi-TM₁₀, quasi-TM₂₀, TE/TM hybrid).

 

Fig. 3 Top-left (long-dashed red outline): single guided mode in a Si waveguide with a 1000 nm × 50 nm cross-section; Otherwise (short-dashed black outline): seven guided modes in a Si waveguide with a 1000 nm × 260 nm cross-section. The color maps are proportional to the energy density computed by the Lumerical FDTD mode solver.

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With the cross-sectional dimensions of the thinned and un-thinned parts of the waveguide determined, a second set of Lumerical simulations were performed to determine the optimal vertical taper length for impedance-matching from 260 nm to 50 nm. Figure 4(a) shows that a length of ~6 µm offers a good compromise between losses (~98% transmission for a single pass) and footprint (taper length).

 

Fig. 4 (a) Bidirectional dependence between quasi-TE₀₀ mode transmission efficiency and taper length, for a 1 µm wide taper going from 50 nm to 260 nm in height; (b) Dependence between transmission efficiency and propagation distance through the thinned region of a TE-Pass filter for the quasi-TE₀₀ and quasi-TM₀₀ modes. Simulations in (b) take reflections off the Si handle substrate into account.

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To complete the design, Lumerical simulations were carried out to estimate the quasi-TE₀₀ and quasi-TM₀₀ mode transmissions with respect to propagation distance in the thinned region. The data shown in Fig. 4(b) demonstrate that while the quasi-TE₀₀ mode transmission stays roughly constant at around 93.8% up to a distance of 200 µm, the quasi-TM₀₀ mode transmission decreases rapidly and tends towards zero (0.21% at 200 µm). Figure 5 shows the electric field amplitude squared profile of the quasi-TE₀₀ and quasi-TM₀₀ modes in the thinned waveguide. As seen in the figure, the quasi-TE₀₀ is strongly guided throughout – the oscillations at the output are due to mode beating between the quasi-TE₀₀ and the quasi-TE₂₀ modes (when going from 50 nm to 260 nm over a 6 µm distance, FIMMPROP simulations show that 0.38% of the input power is coupled to the quasi-TE₂₀ mode.). As for the quasi-TM₀₀, it dissipates rapidly through radiative losses.

 

Fig. 5 Vertical cross-section of the electric field magnitude squared (|E|²) computed by Lumerical at the center of the 200 µm TE-pass filter, for both polarizations (ordinate and abscissa units are in microns). Simulations take reflections off the Si handle substrate into account.

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3. Device fabrication

TE-pass filters were fabricated on SOI substrates with a 260 nm device layer. The buried oxide (BOX) layer was 2 µm thick and the Si handle was 675 µm thick. A 1.8 µm SiO₂ layer was first deposited by plasma enhanced chemical vapor deposition (PECVD) followed by an 80 nm Si₃N₄ mask layer (also by PECVD). Two photolithography steps were required to fabricate the TE-pass filters. Mask 1 defined the regions to be thinned, where several openings defined a range of thinned waveguide lengths (50, 100, 150 and 200 µm). Mask 1 also had one large non-device opening (12 mm × 12 mm) used to measure the thickness of the Si device layer by ellipsometry during the thinning process. Mask 2 defined the 1 µm wide waveguides boundaries. Both masks had alignment marks to correctly place the waveguides on the different thinned regions.

Fabrication proceeded as follows: standard contact photolithography was carried out on the Si₃N₄ layer using mask 1 with inductively coupled plasma (ICP) etching. The remaining photoresist was removed. The PECVD and the Si device layer thicknesses were measured by ellipsometry and the measurements used to calculate the wet thermal oxidation time (see section 2). After oxidation, the PECVD and grown SiO₂ layers were etched with an HF solution. With these layers removed, more precise ellipsometry measurements could be carried out to determine if any additional thinning was required to attain the desired result. If required, the Si device layer could be fine-tuned with plasma O₂ and BOE etching. Figure 6 shows typical ellipsometry thickness measurements throughout the process steps.

 

Fig. 6 Ellipsometry measurements of the Si device layer thickness following thinning steps.

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Once the optimal thickness was attained, standard contact photolithography with mask 2 was used to define the width of the waveguides. The pattern was etched in the Si device layer by ICP. Afterwards, samples were cleaned and covered by 2 µm of PECVD SiO₂. Rapid thermal annealing (RTA) is performed at 450 °C during 5 min to desorb H₂ trapped in PECVD SiO₂. A resist was added to protect the samples during thinning of the substrate. This step helps cleaving precision and generally leads to better facet quality.

4. Experimental results

Fabrication according with the above procedure produced TE-pass filter devices with dimensions very close to the design objectives (Fig. 6 shows a final thickness measurement of 49.9 nm). Scanning electron microscopy (SEM) pictures show that the waveguides have a width between 1100 nm and 900 nm (a typical SEM facet image is shown in Fig. 7(a)). The cross-section of the taper between a thinned and an un-thinned regions reveals a taper length of ~5.3 µm with a very smooth slope (Fig. 7(b)). The side wall roughness of the waveguides, however, is higher than expected with peaks as large as 30 nm, increasing propagation losses as discussed below.

 

Fig. 7 SEM picture of (a) facet of a waveguide and (b) cross-section of a vertical taper.

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The devices were characterized with the setup shown in Fig. 8. The linearly polarized tunable laser output was set to a wavelength of 1550 nm. Polarization of the light injected into the devices was controlled by monitoring the output of the lensed polarization maintaining (PM) fiber with a polarization analyzer and adjusting the fiber rotation. The injected intensity was controlled by monitoring the output of the lensed PM fiber with a photodetector and adjusting the laser output. This setup enabled the injection of equal intensity TE and TM polarizations into the devices by butt coupling. The output light from the devices was collected with a 50X objective (NA = 0.6), passed through a polarization filter, and measured with an IR camera (MicronViewer 7290A connected to a National Instruments PCI-1405 acquisition card). The captured images (640 × 480, 8-bits depth, grayscale) were averaged (20 images captured at 1 Hz frame rate) and the image data were linearized by removing the gamma correction in post-processing (the gamma correction could not be disabled in the camera). Moreover, on each image, the background noise was removed and the spot was isolated by zeroing out every pixel outside a radius sufficiently large to enclose the entire spot (15 pixel radius). Sample pictures are shown in Fig. 9(a) and Fig. 9(b) for the TE and TM polarizations, respectively.

 

Fig. 8 3D schematic diagram of the optical setup used to characterize the TE-pass filters. The optical fiber is connected to a tunable laser with a linearly polarized output.

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Fig. 9 Example of the output of a 200 µm length TE-pass filter for (a) TE polarization and (b) TM polarization. The scale of the color map is the same for both polarizations. (c) Dependence of TM/TE intensity ratio on the thinned waveguide length. The triangular dots represent experimental measurements whereas the circular dots are simulation results.

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Values proportional to the total optical intensity in each polarization, V_TE and V_TM, were estimated by summing the pixels in each image. Since the output intensity for the quasi-TE₀₀ mode was essentially constant for the different taper lengths (see Fig. 4(b)), V_TE was used as a normalization factor for comparative performance analysis. Also, since the waveguides do not have a square aspect ratio, injection losses by butt-coupling were polarization-dependent. Accordingly, V_TM values were corrected for this discrepancy with a factor, α, calculated with Lumerical (α = 0.582). Figure 9(c) shows the resulting output intensity ratios in percent between polarizations, αV_TM/V_TE, for the 4 thinned waveguide lengths tested.

Figure 9(c) clearly shows the filtering effect. The difference between experimental and simulated data is believed to be caused by the multi-mode behavior of the input and output waveguides and the propagation losses. While the multi-mode effects are hard to predict in the present case, adjustments to the data to account for the propagation losses would help diminish the gap between the experimental and simulation data since the propagation losses, caused by the side wall roughness, are higher for the TE polarization.

5. Conclusion

This paper demonstrated a modified LOCOS process for precisely thinning the SOI device layer to form optimal waveguides of different application-specific heights. It also creates the long and smooth vertical tapers (~5.3 µm long for ~210 nm of height) required for impedance matching between sections of different heights while remaining CMOS compatible. The fabrication process is mainly limited by the pad oxide where control of Si thinning decrease with its thickness. The process was validated by fabricating a TE-pass filter. The developed technology shows great potential for large-scale low cost integration of optical devices with heterogeneous vertical dimensions on a common substrate.