1. Introduction

The silicon-on-insulator (SOI) platform is promising for large-scale, high-density photonic devices integration that attracts both academics and industry [1–3]. Complementary mental-oxide-semiconductor (CMOS) compatible processes are of special interest since devices or systems fabricated with them can be readily integrated with on-chip microelectronics. However, unlike electronic circuits where electrical routing can be accomplished flexibly on multiple layers, optical routing is fundamentally banned from multi-layer integration due to limitations of optical mode coupling and cost control. In order to reach high-volume photonic systems on a single chip, use of the waveguide crossing is unavoidable. It is one of the key building blocks for all silicon photonics platforms. However, directly crossing two waveguides causes severe light scattering, crosstalk and multi-modes-excitation [4]. Prior work has been done to improve crossing performances, based on mode expansion [4–7], optimized angles [8], multimode interference (MMI) [9–11], Bloch waves [12,13], polymer waveguide bridges [14], sub-wavelength gratings [15], and photonic crystals [16].

Sub-0.2 dB insertion loss and −40 dB crosstalk are the typical performance metrics for the state-of-the-art compact crossings fabricated in SOI CMOS process [5,6,11]. While these crossings have already been integrated into on-chip photonic systems, insertion loss around sub-0.02 dB is greatly desired by the silicon photonics community for use in large-scale integration. Over the past decade, there has been a rapid growth in photonic component count and system complexity of silicon photonic systems [1]. As system size increases, more crossing structures will be required for neat and efficient optical routing and building large scale networks-on-chip (NoC) [17]. Several works have achieved such low loss crossings with different methods. For example, insertion loss as low as 0.015 dB/crossing was reported in an 8 × 8 silicon optical switch [7], but the taper length of the crossing is about 80 μm to expand the mode size to 6 μm with minimum loss. Such a large crossing is unattractive for large-scale photonic interconnects. In another work, sub-wavelength gratings [15] were explored to reduce the loss to 0.025 dB/crossing but a 0.3 dB taper loss will be introduced when connected to a ridge waveguide. Another approach reported is to design a crossing array instead of a single crossing device with Bloch wave method. Recently, Zhang et. al. [13] reported 0.02 dB/crossing loss in a 101 × 101 crossing array fabricated on a 250 nm SOI with electron beam lithography (EBL). However, with the feature size of the Bragg-grating-like subwavelength nanostructure as small as 50 nm, the performance of such a device still remains unknown when transferred into a CMOS photonic process where 193nm or 248nm Deep-UV lithography is typically used. For such crossing arrays, waveguide routing is also intuitively inconvenient when large-scale, high-complex photonic systems are involved. It would be much more routing efficient to lay down a single crossing wherever needed, especially for complex photonic systems.

As one of the most basic building blocks, performance uniformity is definitely a critical performance metric, but few papers report this important metric.

In summary, an ultralow loss single crossing with compact size, stable performance and CMOS process compatibility is greatly desired yet no such crossings with sub-0.02 dB loss had been reported to the best of our knowledge.

In this work we report two compact, ultralow loss, single layer, broadband crossings with optimized center wavelength at 1550 nm and 1310 nm, respectively. Cross-wafer average insertion loss of 30 dies (i.e., reticles) is − 0.0278 ± 0.0092 dB/crossing for the device centered at 1550 nm and 0.0168 ± 0.0047 dB/crossing for the 1310 nm device. For both crossings, the device footprint is 9 × 9 μm², crosstalk is below −37 dB and wavelength dependence is less than 0.09 dB in a 60 nm range with respect to center wavelength.

2. Design and fabrication

2.1 Design and optimization

The design methodology in this work was based on our previous report of a low-loss waveguide crossing at 1550 nm [6]. Note that similar crossing design was earlier reported by Sanchis et. al. [5] on 250 nm thick top silicon SOI wafer. Our platform offers a 220 nm thick SOI wafer. Particle swarm optimization (PSO) coupled to the finite-difference time-domain (FDTD) method was utilized to generate the optimal design. This method has already proved its strong capability in designing compact, multiple-parameter optical devices [6,18]. Schematic layout of the crossing is shown in Fig. 1(a).The crossing geometry is defined in the way similar to Fig. 1 of Ref [5]. It is constituted of four identical tapers respectively orientated at east, west, south and north with a shared center point. The taper length, L, is fixed to 4.5 μm but the width is defined by 13 variables, i.e., w1, w2, … to w13 as indicated in Fig. 1(a). These 13 variables are equally distributed along the taper length, with a spacing of 0.375 μm (4.5 μm/ 12). The final device geometry is defined by spline interpolation of the width variables. Four short straight ridge waveguides are appended to the tapers to lead-in/lead-out light. During optimization, w1 and w13 are fixed as the same as the waveguide width, which is 0.5 μm for the 1550 nm device and 0.42 μm for the 1310 nm device. Note that although it looks from Fig. 1(a) that w12 has trivial contribution to the final geometry, it is actually as important as other width variables in the very beginning of optimization when one has little idea of what the final result would be. The initial value is set to be the same as waveguide width. As the crossing geometry evolves, w12 naturally increases and merges into the cross-sectional region. The width variables were sometimes manually restricted to achieve smooth structures (wavy structures are usually formed by the nature of multiple-parameter optimization) and pass the design rule check (DRC) required by foundry. These two devices were optimized for TE0 mode.

 

Fig. 1 (a) Schematic device layout. The device is symmetric and constituted by four identical tapers. The taper is defined by spline interpolation of w1 to w13. (b) Log-scale Electric field distribution at 1550 nm from FDTD simulation. (c) Mode evolution of the left taper with light input from the left side.

Download Full Size | PDF

Optimization figure of merit (FOM) for the crossing is defined as normalized TE0 power transmission minus crosstalk and reflection at a certain wavelength, written as FOM_λ. In order to achieve a wavelength insensitive device, we first chose 11 wavelength points across a 100 nm range (centered at 1550 nm and 1310 nm for the different devices, respectively) and take the average of FOM_λ as FOM_avg. Maximizing FOM_avg dramatically reduces the wavelength sensitivity as well as crosstalk and reflection. The device was then further optimized at the center wavelength. A so-called 2.5D propagator method was first run to quickly reach an approximate optimization state. The 2.5 D propagator first takes in vertical modes of the core waveguide structure of a certain material, over a desired range of wavelengths. Then by calculating the corresponding effective 2D indices, the 2.5D propagator reduces the 3D problem into an effective 2D problem. The 3D-to-2D effective index conversation method can be found in Ref [19]. A 3D FDTD simulation was then introduced to achieve the accurate optimization state. Simulation codes for both methods are commercially available [20].

In Fig. 1(b), we show a contour plot of electric field distribution of 1550 nm crossing at 1550 nm. Note that the color bar is in log-scale in order to show the weak scattering and crosstalk field. As can be seen, peak magnitude of E-field in the two crosstalk tapers is ~− 17 dB. No scattering field with magnitude above − 24 dB can be observed outside the crossing area.

The key issue in a designing waveguide crossing is to converge the mode pattern at the cross-sectional region to minimize light scattering and crosstalk. As can be clearly seen in Fig. 1(c), mode profiles are first expanded from TE0 mode (x = 0 μm) to TE1-like mode (x = 2 μm) and then converged again as TE0-like mode at the crossing center (x = 4.5 μm). The mode pattern at the center can be regarded as a close replica of the input waveguide mode, which is a typical feature of self-imaging due to multimode interference. The observed crosstalk pattern is also a result of multimode interference. The well-engineered taper helps adiabatically convert TE0 mode into multimode and tailor the modes between the multimode region and the crossing center region to reach the well converged mode pattern at center.

For FDTD simulation, the number of mesh points per wavelength (ppw) is a major consideration for the meshing algorithm. After doing a mesh grid sweep, we found 14 ppw is the optimal value considering the tradeoff between simulation accuracy and time cost. The FOM difference was within 1.1% compared with 26 ppw mesh grid but simulation speed was more than 6 times faster. The output power of crossing was monitored in y-z plane centered at the waveguide center, with a monitor size of 4 μm × 2 μm. For both 1550 nm and 1310 nm crossing, we tested the influence of monitor positions along the x-axis and found the difference of FOM_λ at the central wavelength was within 0.2%. Particle warm population was set to 20 and 60-70 generations were generally needed to reach a converged FOM.

The length L is crucial for a taper since it determines how efficient the mode conversion can be [21]. Guided modes are not able to fully converted to each other given a short L, as a result light will be scattered instead of keep guided as it propagates along a taper. In our previous work [6], a 3 μm long taper was selected and it turned out the simulated FOM₁₅₅₀ saturated at 0.965 (i.e., − 0.154 dB), with experimental device performance of − 0.18 dB. However, the benefit to FOM drops quickly after L exceeds a certain value. Note that in Ref [7], even for a crossing with L ~80 μm, the insertion loss, − 0.015 dB, is not much improved from our design. Long L is also undesirable for high-density silicon photonics integration. After several tries, we chose L = 4.5 μm as the optimal value. As for the number of width variables, 13 is a moderate number for the crossing with L = 4.5. Fewer width variables would have difficulty defining the crossing geometry while significantly more width variables would not notably improve the FOM but would harm the convergence speed of PSO algorithm.

2.2 Simulation result

Figure 2 shows the simulated transmittance, reflection and crosstalk for the 1550 nm device (Fig. 2(a)) and 1310 nm device (Fig. 2(b)). Curves in blue represent total normalized light power while those in purple mean light power for TE0 mode only. For transmittance, the variation in a 100 nm range is around 0.1 dB for both crossings. It’s also clearly shown in the figure that the center wavelengths of 1550 nm and 1310 nm are the most optimized wavelengths. Reflection in Fig. 2(a) is slightly better than that in Fig. 2(b), but even the maximum total reflection power in Fig. 2(b) is relatively small (− 28 dB, i.e., 0.16%). Total crosstalk power is below −33 dB for both crossings in the simulated 100 nm ranges. Crosstalk of TE0 mode is even one times smaller, well below − 50 dB. For the 1550 nm crossing, 3D FDTD simulation gave FOM₁₅₅₀ = 0.996 (i.e., − 0.017 dB) and FOM_avg = 0.990 (i.e., − 0.043 dB), while for 1310 nm crossing, FOM₁₅₅₀ = 0.971 (i.e., − 0.128 dB) and FOM_avg = 0.963 (i.e., − 0.164 dB). In a word, simulation results in Fig. 2 demonstrated two low-loss, low-crosstalk and broadband single layer waveguide crossings centered at 1550 nm and 1310 nm respectively. The detailed crossing geometry parameters are provided in Table 1.

 

Fig. 2 Simulated transmittance, reflection and crosstalk of (a) 1550 nm crossing and (b) 1310 nm crossing in a 100 nm range.

Download Full Size | PDF

Table 1. Crossing geometry parameters (μm)

View Table

It’s worth pointing out that the crossings are insensitive to the SOI silicon thickness and thus highly applicable to other SOI platforms. For example, with the same x-y plane geometries reported in this work, 3D FDTD simulation showed very good FOM: FOM_{1550_} = 0.984 (i.e., − 0.070 dB) and FOM₁₃₁₀ = 0.954 (i.e., − 0.205 dB) for 250 nm thick silicon and FOM₁₅₅₀ = 0.962 (i.e., − 0.168 dB) and FOM₁₃₁₀ = 0.935 (i.e., − 0.292 dB) for 300nm thick silicon. One can expect further improvement by further optimizing the crossings on these SOI platforms.

2.3 Device fabrication

Devices were fabricated using a CMOS-compatible process on an 8-inch SOI wafer at the Institute of Microelectronics (IME)/A*STAR through an OpSIS multi-project-wafer run. The top silicon thickness is 220 nm, on top of 2 μm buried oxide (BOX). Devices were patterned by 248 nm deep UV photolithography, followed by dry etching. The top silicon was completely removed outside the crossing area, left with a 220 nm thick single layer device. Tiles were used around the devices with reasonable distances away to achieve a certain filling ratio. Finally a 2.3 μm oxide-cladding layer was deposited on top of the silicon layer.

3. Measurement and discussion

3.1 Test structures

Testing farms with gradually increased number of cascaded crossings were utilized to extract insertion loss. A three terminal structure with grating coupler (GC) connected was used to characterize the crosstalk by measuring spectrum of any two adjacent GCs. GCs that vertically coupled light on and off chip enabled the cross-wafer measurement. The pitch of two adjacent grating couplers is 127 μm, determined by the pitch of the fiber array. A clear layout and fabricated micrograph of the grating coupler design was shown in [22]. The GC is designed to support TE0 mode, which is also the mode that our crossings optimized to work for. If other modes exist simultaneously, such as TM mode, they will interference with TE mode and create ripples on spectrum which were not evident in this work [18]. The die size on the wafer is 2.5 cm × 3.2 cm, splitting the 8-inch wafer into 31 dies. Excluding one incomplete die, a total of 30 dies were tested. An Agilent 81600B tunable laser was used as the laser source.

3.2 Device characterization

Figure 3(a) shows a small sample of measured experimental spectra (dot curves) of the 1550 nm crossing with 0, 25, and 55 crossings. Note that crossing number = 0 also means the reference GC loop, i.e., two GCs routed by a U-turn waveguide. The GC loop introduces a baseline loss of about − 16 dB at its peak, independent to crossing loss. It’s worth noticing that the spectra are not notably deformed as crossing number increased, even up to 55 crossings. This indicates that although higher order modes are excited inside the crossing tapers, as we discussed earlier in Fig. 1(c), an insignificant multi-modal power reaches the output. Almost all the high order modes converted back to TE0 mode by the output point. In this way, mode pattern and light energy are nearly fully conserved. This is an important merit for a highly qualified crossing and is extremely desirable for large scale optical interconnects.

 

Fig. 3 Device performance characterization. (a) Experimental (dot curve) and fit (solid curve) spectra at different cascaded 1550 nm crossings. Inset is a fabricated test structure with 10-cascaded crossings. (b) Peak power (dots) extracted from measured spectra for 1550 nm crossing (blue) and 1310 nm crossing (purple). The slope from linear fitting of peak powers represents insertion loss per device. (c). Experimental spectra of reference GC loop (black) and crosstalk (blue). Inset is fabricated crosstalk test structure. (d) Insertion loss variation in a 60 nm range after de-embeding the spectrum of the reference GC loop.

Download Full Size | PDF

We then fitted each measured spectrum with parabola (solid curves in Fig. 3(a)) in a 40 nm range centered at its peak wavelength. The micrograph of fabricated cascaded crossing structure is shown in inset of Fig. 3(a). The fitted peak powers, shown in Fig. 3(b), were then utilized to extract the insertion loss of each crossing in dB/crossing. Blue dots stand for 1550 centered crossing while purple ones stands for the 1310 nm device. The insertion loss obtained from linear fitting in Fig. 3(b) is − 0.0246 dB for the 1550 nm crossing, almost an order of magnitude lower than typical crossing loss fabricated in CMOS process. The 1310 nm crossing surprisingly has an even lower loss, − 0.0173 dB, due to fabrication proximity effect, better than simulation results.

Crosstalk spectrum (the blue curves) of 1550 nm crossing is shown in Fig. 3(c), measured from the left two adjacent GCs as in inset of Fig. 3(c). The crosstalk is not wavelength sensitive and measured to about − 37 dB, low enough for practical applications. For 1310 nm device, similar results were observed. Note that the crosstalk signals lies at the border of the noise floor of our testing system. Real crosstalk should be even smaller than this value.

By de-embedding the reference GC spectrum, we were able to get the pure wavelength-dependent crossing spectrum. For both designs, we chose the spectrum of 55-cascaded crossings – largest number in our layout – to do de-embed since device flaws will be accumulated but random factors will be suppressed as device number increases. De-embedded results were then divided by crossing number 55, to show the performance of a single device, as presented in Fig. 3(d). In a 60 nm range, the variation of 1550 nm crossing is as low as 0.05 dB with smooth spectrum. For the 1310 nm device, the variation is about 0.035 dB with some small ripples. The ripples indicate that some optical modes other than TE0 mode come out of the crossing. However, the ripple magnitude is within 0.012 dB, which is still negligible for most applications.

3.3 Performance uniformity

Performance uniformity is an important metric for any device aimed for system applications, especially for devices that act as basic building blocks in silicon photonics, such as grating couplers, y-junctions and crossings. The deviation of performance can be from either the SOI wafer itself, such as thickness variation of top silicon, or the fabrication process flow deviation on each die.

We performed cross-wafer measurement for insertion loss on 30 dies. Statistical analysis is summarized in Fig. 4. The contour plot clearly shows the performance variation across the wafer for each crossing. The histogram on the right shows the loss distribution in terms of dB. As can be seen, the distribution more or less appears Gaussian for both devices. For the 1550 nm crossing, we calculate that the loss is − 0.0278 ± 0.0092 dB/crossing, bounded between − 0.0559 and − 0.0178 dB. The 1310 nm device loss is − 0.0168 ± 0.0047 dB/crossing, bounded between − 0.034 dB and − 0.0028 dB.

 

Fig. 4 Cross-wafer measurement. Contour plot (left part) and histogram analysis (right part) of insertion loss distribution for (a) 1550 nm crossing and (b) 1310 nm crossing.

Download Full Size | PDF

Cross-wafer wavelength variation was calculated as in Fig. 3(d). The result is 0.072 ± 0.022 dB for 1550 nm crossing in a 60 nm range. The variation for 1310 nm crossing is 0.087 ± 0.027 dB. Crosstalk was measured on five dies – (0, 0), (−2, 0), (2, 0), (0, −2), (0, 2), which are evenly distributed across the wafer. All crosstalk spectra were found at noise floor. The crosstalk from five-die analysis is bounded between −40 and −35.6 dB with an average of −37.5 dB for 1550nm-centered crossing. For 1310nm crossing, the upper bound of the crosstalk value is between −34.1 and −43.6 dB with an average of 37.5 dB. Real crosstalk is likely to be even lower.

The above cross-wafer analysis confirmed that the two crossings demonstrated in this work are fabrication insensitive, making them reliable component of a complex integrated photonic system. Taking 1550 nm crossing for example, a system containing 50 × 50 mapped crossings already have the ability to include 2500 other devices and yet the maximum loss contributed from crossing is estimated to only − 1.39 dB (− 0.0278 dB × 50). Assuming all input light sources are identical in such a system, the maximum crosstalk is still about −20 dB or less (smaller than 1% of the input light) after being enhanced 50 times (i.e., increased about 17 dB). Moreover, a pure 50 × 50 crossing matrix only consumes an area of 500 × 500 μm2 (including 1 μm long adjunct waveguide for each crossing), still small compared with current integrated photonic systems. Therefore, with these two crossings, integrated photonics designers can almost intersect waveguides freely to a very large scale, without worrying about energy loss, crosstalk and higher order mode interference.

3.4 Optical proximity correction

The cross-wafer loss variation is relatively low considering the wafer thickness variation and fabrication proximity effect at 248 nm wavelength. However, optical proximity correction (OPC) [23], which is used in microelectronics industry as a resolution enhancement technology (RET), if applied to silicon photonics, can help making photonic device geometry more predictable and thus further improve the performance as well as stability for a lot of geometry sensitive photonic devices [24,25]. This technique is expected to be important for future work in this area. Despite data not currently available for these two specific crossings, evidence has been observed in a different crossing design on the same wafer. The crossing mask was engineered with OPC. Analysis data on five dies showed that the insertion loss improved from − 0.506 ± 0.133 dB/crossing to − 0.184 ± 0.012 dB/crossing, which is closer to the simulation result. For this crossing, OPC not only improved performance, but also decreased the standard deviation, indicating more uniformly fabricated geometries across the wafer. Further data is available in the supplementary materials. The OPC model was built from the source parameters provided by the fab. In future, experimental data from specific test structures will be gathered to build a more concrete and precise OPC model that should help improve fabrication stability and predict device performance.

4. Conclusion

Two compact, ultralow loss, and single layer crossings were demonstrated with operation center wavelengths at 1550 nm and 1310 nm respectively. The devices were fabricated in a 220 nm thick SOI CMOS process with 248 nm photolithography. Cross-wafer measured insertion loss for the 1550 nm device is − 0.0278 ± 0.0092 dB/crossing, comparable to the state-of-art results demonstrated by EBL and almost one order of magnitude smaller than the current results in a CMOS process. A 1310 nm crossing, which is very necessary for SOI platforms, was also designed and has an even smaller insertion loss: − 0.0168 ± 0.0047 dB/crossing. The authors believe that this is the first reported ultralow loss waveguide crossing at 1310 nm. The devices are wavelength insensitive within a bandwidth of 60 nm. Crosstalk of both devices is less than − 37 dB. The crossings developed in this work remove the restrictions on optical waveguide intersections and pave the way for interconnecting large scale, high-density, high-complex silicon photonics systems.