1. Introduction

Leveraged by the proliferation of complementary metal-oxide semiconductor (CMOS) technologies, silicon photonics has gained a significant position in the field of optical communication [1], optical computing [2], quantum computing [3], optical beam forming [4], and bio-sensing [5].

A critical function in any silicon photonic circuit is photodetection, particularly when integrated with internal amplification, to address the need to work within a limited link budget. There have been several reports of amplified detection including Si/Ge avalanche photodetectors (APDs) [6–9] and all-silicon APDs [10–12]. Si/Ge photodetectors are disadvantaged by a relatively large leakage current, attributable to the lattice mismatch at the Si/Ge interface [13,14]. Conversely, all-silicon photodetectors suffer from relatively low responsivity due to silicon’s low optical absorption coefficient at 1550 nm even with sensitization via deep levels [11,15,16].

A phototransistor operates as a photosensitive transistor, effectively combining the properties of both a photodiode and a bipolar junction transistor (BJT). The conductivity of a phototransistor is modulated by the base current, which originates from the electron-hole pairs generated from the active area upon optical excitation. Phototransistors achieve high responsivity due to internal photocurrent gain, eliminating the need for low input impedance between the phototransistor and external amplifiers, leading to a simplification of the overall circuitry [17]. The impedance of phototransistors can be tuned to adjust the gain and diminish device noise, making them ideal for monitoring optical signals across a large dynamic range of intensities. Moreover, such a high-responsivity phototransistor eliminates the transimpedence amplifier (TIA) element from the subsequent circuit chain, which leads to reduced system design complexity and an improved system power budget [18]. In some applications, proposed high-gain phototransistors can be directly terminated using a broadband passive impedance matching network, diminishing the need for implementing successive TIAs and limiting amplifier (LA) circuit blocks.

In addition to responsivity, low phase noise is a desirable feature in numerous applications, including LIDAR [19], high-quality RF or microwave signal generation [20], frequency comb generation [21] and photonics based quantum applications [22]. Low phase noise and a clean RF spectrum without any harmonic distortion are crucial design parameters for precise range and speed detection [23–26]. Also, excess phase noise from photodetectors overloads the successive signal processing units, additional high-quality factor (high-Q) photonic filtering, and constrain the TIA design specifications [10, 11]. Similarly, phase noise in photodetectors is a major bottleneck in RF-photonics, time and frequency metrology, and photonic low-phase noise microwave generation or in frequency converter systems [12, 13]. Achieving both high responsivity and low detector phase noise performances concurrently is challenging.

Ultra-high responsivity ranging from $10^5$ to $10^7$ A/W has been demonstrated for phototransistors with different material systems including hybrid graphene-perovskite [14], InGaAs [3], and inorganic/organic hybrid materials [15]. However, there has been very limited work on phototransistors on a silicon photonics platform. Responsivities of 42 A/W at 1V [16], 14 A/W at 1.5 V [17], and 53 A/W at 1 V [18] have been achieved for waveguide integrated phototransistors using a commercial silicon foundry.

Here we demonstrate a Si/Ge phototransistor that operates at the conventional optical band centred at 1550 nm, with high responsivity, low dark current and low phase noise. The devices are fabricated using a standard silicon photonics fabrication technology without modification or post processing. The key innovation compared to previous work is the introduction of floating p⁺-doped regions beneath the photosensitive germanium, allowing the passive manipulation of the electric field, with concomitant suppression of dark current generated at the Ge-Si interface [27].

This article is organized as follows. Section 2 describes the device design and fabrication followed by experimental characterization in Section 3. It also explains the effect of the p⁺-doped regions in terms of responsivity and dark current performance. Finally, a conclusion and outlook is provided in Section 4.

2. Method

2.1 Operational principle

The device is a waveguide integrated phototransistor designed with an n-p-n configuration with two floating p⁺-doped regions beneath the germanium epitaxial layer as shown in Fig. 1. P_x and P_width denote the distance from the device center to the inner edge of the p⁺-doped regions and the width of the p⁺-doped regions. The low-doped i region, the n⁺⁺ region within the Ge, and the n⁺⁺ region within the Si act as the base (B), emitter (E), and collector (C) of the phototransistor, respectively. The emitter is heavily doped to supply ample carriers during device operation.

 

Fig. 1. Cross-sectional diagram of the n-p-n structure of the Si/Ge photodetector with electric field and current density (J) simulation of the photodetector at a forward bias of 2 V_ce. Voltage is applied on the emitter and the right side collector only in the simulation. Bottom shows the band diagrams of the devices with a cutline at the Si/Ge interface demonstrated in the current density plots. Left, without p⁺-doping; right, with p⁺-doping.

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Unlike previously reported waveguide Si-Ge phototransistors [28], the two p⁺-doped regions distributed under the Ge facilitate an increased gain while suppressing the leakage current of the n-p-n structured phototransistor by re-configuring the electric field distribution. The structure is simulated with Technology Computer Aided Design (TCAD) from Silvaco, with electric field and current density shown in Fig. 1 for a forward V_ce of 2V.

The B-E potential barrier’s height is governed by the doping levels of the adjacent regions. With the p⁺-doped regions under Ge, the potential barrier at the B-E junction increases as demonstrated in the schematic band diagram (derived from horizontal cutlines at the Si/Ge interface) in Fig. 1, which effectively restricts the flow of dark current through the base region. The increased potential barrier would force the dark current to follow an alternate route that bypasses the Si/Ge interface as shown in the current density plot (right) in Fig. 1, where the dark current is typically originated due to the Ge/Si lattice mismatch [27] as shown in the current density plot (left), thus significantly reducing the dark current. Importantly, this suppression is achieved without significantly impacting the photocurrent pathway, which is more vertical in nature.

When biased in the active regime, with near infrared light (at 1550 nm) coupling, photo-generated holes in the Ge layer are swept into the base region within the diffusion length, while electrons move toward the collector. The accumulation of holes in the base lowers the B-E energy barrier [29]. Electrons are subsequently injected from the emitter into the base region, contributing to the amplification of the photocurrent. The floating p⁺-doped regions would elevate the potential barrier in the valance band at the base, which increases the base’s capacity to accumulate holes, further raising the potential and amplifying the photocurrent. This interplay between the structural elements and carrier dynamics is crucial for the observed improvement in photocurrent. The internal gain of the photo response and the dark current, determined by the base current (photo-generated carriers), can be adjusted by modulating the intensity of the injected light.

2.2 Device fabrication

Device fabrication was carried out at the Advanced Micro Foundry (AMF) using 193 nm ultraviolet lithography multi-project wafer (MPW) process, facilitated by CMC Singapore Microsystems of Canada. Silicon-on-insulator (SOI) <100> wafers with a silicon thickness of 220 nm were etched to form rib waveguides with a nominal width of 10 µm and a length of 200 µm on top of 2 µm of buried oxide. A silicon taper of 100 µm length was used to couple light from the routing strip waveguide with a width of 500 nm to the rib waveguide of 10 µm width. The doping regions in the silicon layer were formed by the implantation of boron (p-type) and phosphorus (n-type) in the 220 nm thick waveguide region. The i-region in the silicon (base region) is in fact slightly p-doped to a level of $\sim 5-10\times 10^{15}cm^{-3}$ and the floating p⁺-doped regions to a level of $\sim 1\times 10^{19}cm^{-3}$. The width and location of the p⁺-doped regions (P_width and P_x) varied from 0.75 µm to 1.5 µm, and from 0.5 µm to 1 µm, respectively, to investigate the impact of p⁺-doped regions on the device performance. With the total device length and the width of the collector fixed, the distance between the edge of the p⁺-doped region and the edge of the n⁺⁺ region varied from 0 µm to 1.25 µm. The collectors are doped to a level of $\sim 5-10\times 10^{20}cm^{-3}$. A layer of germanium was deposited on top of silicon by selective epitaxial growth with a shallow n⁺⁺ doped layer ($\sim 5-10\times 10^{19}cm^{-3}$) at its top for emitter contact.

2.3 Device characterization

To investigate device optical response, we used light with a wavelength of 1550 nm, sourced from an Agilent 81640A tunable laser. This light, channeled through a tapered single-mode fiber with a 2.5$\pm$0.5 microns spot size, was introduced into the silicon waveguide. For optimal results, we ensured the light maintained a quasi transverse electric (TE) mode, utilizing polarization paddles. The optical power injected from the tapered fiber was adjusted and calibrated using a Thorlab VOA50 variable optical attenuator and an integrating sphere Thorlab PM400 power meter. Optical coupling and transfer waveguide propagation loss resulted in a total loss from fiber to detector of 4 dB.

For DC characterization, a Keithley 2400 source meter was used to control the bias and capture the photocurrent of the devices. The high frequency S₂₁ response of the device were measured with an HP8719C vector network analyzer, where a 1550 nm optical carrier was used to modulate the injected RF sweep signal from the VNA. The devices were set in forward-bias V_ce mode using GS RF probes, facilitated by the Keithley source meter combined with a bias tee. The collector was connected to a positive voltage to reverse-bias the collector-base junction, ensuring that the phototransistor is primed to respond to incident light. Single side band (SSB) phase noise characteristics were measured using a pure RF signal at 1 GHz modulated using an optical carrier at 1550 nm and subsequently the electrical spectrum was measured using a high resolution (5 Hz) electrical spectrum analyzer (ESA). For comparison, data was acquired from devices with different configurations of floating p⁺-doping regions.

3. Experimental results

3.1 Steady-state response

The device operates under both positive and negative V_CE due to the n-i-p-i-n doping structure, which resembles an n-p-n type bipolar phototransistor [30]. Due to the asymmetry of the device geometry and doping, the phototransistor exhibits different electrical characteristics under different biasing polarity. The emitter is more heavily doped than the collector, thus when operating in the forward V_CE regime, the emitter region is able to provide more electrons to tunnel through the base region for extraction by the collector, resulting in significant photocurrent as demonstrated in Fig. 2(a).

 

Fig. 2. a), b) Device dark current, illuminated current, and responsivity under different incident power levels with incident light at 1550 nm; c) responsivity versus optical power at different applied voltage; d) I_ON/I_OFF ratio of the device under different incident power levels.

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The optimized device where the two p⁺-doped regions of 0.75 µm width are separated by a distance of 1 µm, exhibits dark current of 4 nA and 4 µA under V_CE of −1 V and 1 V respectively. An illuminated current of 440 µA and 2600 µA are obtained under these biases when the device is injected with TE polarized light at 1550 nm with a power of −10 dBm, corresponding to a responsivity of 4.4 A/W and 26 A/W respectively. In reverse bias, the lower responsivity arises because the collector is less heavily doped than the emitter, leading to a reduced availability of carriers. It is noted that under these conditions, the phototransistor enters the high injection regime with a relatively high intensity of optical power present in the device. This generates a surplus of minority carriers that are injected into the transistor’s base region, leading to a low photocurrent gain.

The injected optical power was decreased from −10 to −50 dBm using the optical attenuator. The illuminated current decreased from 440 µA and 2600 µA to 56 nA and 10 µA under a forward and reverse V_CE of 1V respectively. However, the device responsivity was increased from 26 to 606 A/W under 1 V V_CE as shown in Fig. 2(b), due to the transition from the high injection regime to the normal operation regime. Compared to previous work on phototransistors fabricated using silicon photonics technology [28] where at −30dBm optical power, responsivity of 232 A/W with a dark current of 45 µA at 5 V, and 42 A/W with 9 µA dark current at 1 V were reported, the optimized device in this work exhibits responsivity of 318 A/W with a dark current of 42 µA at 2.8 V, and 281 A/W with 4 µA dark current at 1 V. Besides, the I_ON/I_OFF ratio (defined as $\textrm{I}_{\textrm{ON}}/\textrm{I}_{\textrm{OFF}}(dB)=20log(I_{\textrm{illumated}}/I_{\textrm{dark}})$) increased to 16 dB and 36 dB at 5 V and 1 V respectively compared to 5 dB from [28].

A maximum responsivity of 1032 A/W was obtained under a forward bias of 2.8 V with an optical power of −50 dBm, where the dark current is 42 µA. This is a significant improvement over previously reported work using a commercial Si photonics platform [28], and the first report of >1000 A/W responsivity on this platform. The responsivity of the device rapidly rolls off above 3 V_CE due to the increase of the dark current. Thus the optimal working regime of the device is between 0.5 V and 3 V under forward V_CE.

Figure 2(c) shows the responsivity at V_CE = 0.5 V and V_CE = 2.8 V versus optical power. The device responsivity decreases as optical power increases due to the increasing injection of carriers in the base region. Despite its high responsivity, the device sensitivity is compromised by the dark current at low optical power levels even in these dark current suppressed designs. As shown in Fig. 2(d), the I_ON/I_OFF ratio drops from 56.0 dB to 7.4 dB at 1 V as the input power is reduced from −10 dBm to −50 dBm.

3.2 Assessing the impact of the floating p⁺-doped regions

The device design introduces p⁺-doped regions with the aim to suppress the dark current and enhance the photocurrent as described in Fig. 1. Figure 3(a) shows the dark current comparison between devices without p⁺-doped regions and with floating p⁺-doped regions (of varying width) beneath the Ge epitaxy. The dark current is reduced by two orders of magnitude from 285 µA to 4 µA at 1V V_CE, and from 575 µA to 2 µA at −4V V_CE for device with p⁺-doped regions of 1 µm width and 1 µm separation. With p⁺-doped regions, illuminated current (Fig. 3(b)) increased from 1.3 mA to 1.5 mA and 1.7 mA at 1 V V_CE with −10 dBm optical power by introducing the p⁺-doped region under Ge layer with widths of 1 µm and 0.7 µm, respectively. This is explained by the band adjustment in the device. Photo-generated holes are drifted to the base region in the electrical field with a forward V_CE bias, resulting in a higher concentration of holes, which leads to a higher bias on the base-emitter junction and a lower potential barrier. Consequently, more electrons can be injected from the emitter to the base region, contributing to an increased photocurrent.

 

Fig. 3. a) Dark current, b) illuminated current (−10 dBm optial power), for devices with different geometries (without p⁺-doped regions, with 1 µm and 0.75 µm width p⁺-doped region); device dark current and responsivity comparisons with c) varying p⁺-doped regions distances, and d) varying p⁺-doped region widths.

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The increase in photocurrent and decrease in dark current collectively contribute to the increase of the device responsivity from 20.5 A/W to 28.9 A/W and 33.6 A/W at −10 dBm with floating p⁺-doped regions of 1 µm and 0.75µm widths respectively. We also note that the dark current can be suppressed to even lower values of less than 1 µA at 1 V V_CE by increasing the distance between the two p⁺-doped regions from 1 µm to 2 µm, which, however, would also significantly decrease the photocurrent of the device to approximately 500 µA, resulting in a lower responsivity.

The geometrical details of the p⁺-doped regions, particularly their width and separation, have a significant impact on the performance metrics of the phototransistor, as shown in Fig. 3(c) and (d). For devices with p⁺ widths of 0.75 µm and 1 µm, increasing the separation between adjacent p⁺-regions reduces the dark current from a high of 20 µA to less than 1 µA, a trend attributable to the suppression of the carrier transport channel. However, this comes at the cost of responsivity, which also drops from an initial 15 A/W to below 5 A/W. Reducing the separation between the p⁺ regions, while maintaining their individual widths, effectively narrows the high potential barrier regions, as depicted in Fig. 1. This narrowing makes it more challenging for carriers to traverse these barriers directly. Consequently, more carriers are inclined to follow the lower potential barrier path along the Si/Ge interface, which is not within the p+ regions. This shift in carrier path effectively broadens the overall low potential pathway for carrier transportation across the device, enhancing conductivity under both dark and illuminated conditions. This change results in the observed increase in both dark current and photocurrent. Moreover, the expansion of this lower potential pathway predominantly occurs at the Si/Ge interface. This interface is significant due to the excess carriers generated by the Si/Ge lattice mismatch. Therefore, an increase in the interface area not only augments the overall carrier pathway but also intensifies the generation of dark current due to the lattice mismatch-induced excess carriers. The key to optimizing the spacing between p+ regions lie in balancing the trade-offs between dark current and responsivity. The optimal spacing is determined by the specific application’s requirements and its tolerance for dark current.

Conversely, when the separation remains unchanged, narrowing the width of the p⁺-regions leads to a desirable reduction in dark current from 1.2 µA to 0.4 µA, while concurrently improving responsivity from 0.6 A/W to 4.5 A/W. The best balance between these factors is found in a device featuring a 0.5 µm p⁺-region separation and 0.75 µm p⁺-region width.

3.3 Electrical bandwidth and phase noise

The dynamic photodetector response is shown in Fig. 4, where devices with different p⁺-region widths were measured while varying the bias voltage.

 

Fig. 4. a) 3-dB bandwidth for devices with 1 µm and 0.75 µm p⁺-region widths under 1 V_CE; b) phase noise with 1 GHz RF carrier for device with 0.75 µm p⁺-region under different biases of V_CE(1 V, 4 V, and −4 V).

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We observed a small signal −3 dB bandwidth of 1.5 GHz and 1 GHz under forward and reverse bias, respectively, where the frequency responses are slightly higher in forward bias due to lower device resistance. All frequency responses were measured using an electrical vector network analyzer (VNA: HP 8719C) and by measuring the S$_{21}$ scattering parameter directly from the VNA. We used a 1550 nm optical carrier to modulate the injected RF sweep signal from the VNA. We measured a −3dB small-signal bandwidth of 1.5 GHz as compared to the conventional photodiodes with tens of GHz. The small-signal response of the phototransistor is primarily limited by the reversed biased B-C junction capacitance as the device consists of a relatively large B-C junction area. Additionally, the base acts as an input to the phototransistor, hence the large junction capacitance is further enhanced by the Miller effect [31]. Therefore, the device bandwidth is significantly compromised. Nevertheless, this structure offers lower noise current than conventional avalanche photodiodes. Note that the device bandwidth can be improved significantly by reducing its length. For the proposed phototransistor, we have designed it for a length of 200 µm which can further be shortened to a conventional $\tilde{2}0$ µm without sacrificing the photocurrent due to the high optical absorption coefficient of Ge. Such a device modification not only boosts the small-signal bandwidth, but also improves the dark current of the phototransistor.

Single side band (SSB) phase noise characteristic was measured for different bias voltage using a pure RF signal at 1 GHz modulated with an optical carrier at 1550 nm and subsequently the electrical spectrum was measured using a high resolution (5 Hz) electrical spectrum analyzer (ESA) placed after the photodetector. The results are plotted in Fig. 4(b). The measured spectrum density depicts a SSB phase noise of −80 dBc/Hz at 1 KHz offset for an −90 dBc/Hz RF input signal. Such a low SSB phase noise characteristic is viable for application in LIDAR for example, where the phase noise (PN) performance is a paramount design criteria [32].

4. Discussion and conclusion

Table 1 provides a summary of recent results for phototransistors on a silicon photonics commercial platform with various structures and material systems. Each type of phototransistor utilizes a distinct operational principle, leading to varied advantages and drawbacks in terms of responsivity, dark current, bandwidth, and compatibility with Si photonics foundries. The study by Frounchi et al. [33] utilized a Ge BJT structure, achieving a responsivity of 80 A/W at 4V, with a notable bandwidth of 10 GHz. In contrast, Sorianello et al. [28] employed a Si/Ge BJT structure, which exhibited a higher responsivity of 232 A/W at 5V and a minimal optical power requirement of 1µW. Going et al. [34] explored the potential of a Ge MOSFET structure, which, while having a lower responsivity of 18 A/W at 1.75V, showed a bandwidth of 2.5 GHz. The 2D FET structure presented by Fu et al. [35] achieved a high responsivity of $3.5\times 10^4$ A/W at 20V, highlighting the potential of 2D materials in this domain. Ochiai et al. [18] introduced a Si/InGaAs FET structure with an impressive responsivity of $10^6$ A/W at 1V. In the present work, a Si/Ge BJT structure was employed, achieving a responsivity of 1032 A/W and 606 A/W at 2.8V and 1V with dark currents of 42 µA and 4 µA, respectively. Dark current density of $2.1\times 10^{-7}$ A/µm and $2\times 10^{-8}$ A/µm are obtained under these biases for a device with a 200 µm length, which is significantly lower than previously reported devices fabricated with silicon photonics technology.

Table 1. A performance summary of selected phototransistors on silicon photonics platform.

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In summary we have demonstrated a Si/Ge waveguide integrated phototransistor with engineered electric field which operates with high responsivity of 606 A/W, low dark current of 4 µA, and low phase noise of −80 dBc/Hz under a low bias of 1 V for input power of −50 dBm. A high responsivity of 1032 A/W with a dark current of 42 µA was obtained under 2.8 V bias. It should be noted that the bias condition significantly impacts the dark current characteristics and hence the overall interpretation of the device’s performance, particularly in low-light applications where dark current is a significant performance indicator. The p⁺-doping regions under the Ge epitaxial layer, was demonstrated to increase photocurrent gain and suppress the dark current compared to a reference device without the p⁺-regions. Dark current and responsivity can be engineered by varying the location of the p⁺-doped regions. A narrower width of the p⁺ regions may contribute to higher responsivity and lower dark current. A −80 dBc/Hz phase noise response at 1 KHz frequency offset was obtained experimentally. Small signal −3dB bandwidth of 1.5 GHz is mainly limited by the base-collector junction capacitance. High responsivity combined with low dark current and acceptable phase noise enables detectivity of light with a wide range of powers. The device is suitable for monolithic integration with advanced CMOS processes operating under a 2V supply and applications involving optical power of the order of nW range, requiring low dark current and phase noise characteristics.