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Abstract
This paper presents a proposal of the world-first optical multi-context scrubbing operation on a redundant system that can maintain the state of a sequential circuit and the operation continuously without any interruption on a radiation-hardened optically reconfigurable gate array even after a permanent failure suddenly happens on the sequential circuit or a flip-flop by radiation. Up to now, a high-speed optical scrubbing operation has been demonstrated on a radiation-hardened optically reconfigurable gate array. In addition, a multi-context scrubbing operation based on the high-speed optical scrubbing operation has already been demonstrated. Although the multi-context scrubbing operation presents the benefit that it can treat both soft-errors and permanent failures caused by radiation simultaneously, the conventional contributions have never presented how to maintain the state of a sequential circuit after a permanent failure occurs on flip-flops. Therefore, in the conventional multi-context scrubbing operation, all the operations must be restarted from the initial condition each time a permanent failure occurs on a programmable gate array. As a result, conventional multi-context scrubbing operations could not be applied for real-time systems. The proposed optical multi-context scrubbing method that can solve the issue has been experimentally evaluated on a radiation-hardened optically reconfigurable gate array.
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1. Introduction
Very large scale integrations (VLSIs) used for spacecraft, space stations, satellites, and other platforms are constantly affected by high-energy cosmic radiation [1–5]. High-energy cosmic radiation frequently causes single-event upsets (SEUs). Moreover, VLSIs are degraded constantly by total-ionizing-dose effects. Eventually, some transistors on VLSIs are permanently ruined. Therefore, space systems require VLSIs with high soft-error and high total-ionizing-dose tolerances.
Currently, field programmable gate arrays (FPGAs) are used widely for space systems. However, FPGAs have an important shortcoming that their configuration circuit is extremely vulnerable to high-energy cosmic radiation in terms of soft-error and total-ionizing-dose tolerances. Therefore, to increase the soft-error tolerance, various scrubbing operations have been applied for the configuration circuit of FPGAs [6–10]. Nevertheless, since current FPGAs use a serial configuration circuit as presented in Fig. 1 so that such scrubbing operations based on the serial configuration architecture become very slow, the soft-error tolerance of current FPGAs even with any scrubbing operation is not good. Moreover, in current FPGA systems, in addition to soft-errors on FPGAs, soft-errors on a serial read-only memory (SROM) must be considered since scrubbing operations are always executed along with a SROM. In addition, the serial configuration architecture is very weak in terms of permanent failure caused by radiation. Even if only one transistor in the serial configuration circuit on an FPGA is broken by radiation, the serial configuration circuit fails. The probability of the configuration circuit failure is extremely high because the serial configuration circuit area is about 40 ${\% }$ of an FPGA chip.
Fig. 1. FPGAs have a serial configuration architecture. Scrubbing operations based on the serial configuration architecture are invariably slow. Each configuration procedure requires a few hundred milliseconds.
Therefore, radiation-hardened optically reconfigurable gate arrays (RHORGAs) that consist of a holographic memory, a laser-array, and a programmable gate array VLSI have been proposed to improve the slow scrubbing operation on FPGAs and to treat permanent failure caused by radiation as shown in Fig. 2 [11,12]. The RHORGAs have benefits that soft-errors never occur on their holographic memory and holographic memory’s total-ionizing-dose tolerance is much higher than that of SROMs [13]. In the architecture, a lot of configuration contexts are stored on a holographic memory and the configuration contexts can dynamically be programmed onto a programmable gate array VLSI. Since the programmable gate array VLSI has many photodiodes to realize an optical parallel bus between the holographic memory and the programmable gate array VLSI, a high-speed dynamic reconfiguration is possible. Up to now, by exploiting the high-speed dynamic reconfiguration capability, a 50 – 70 ns period optical high-speed optical scrubbing operation has been demonstrated on a RHORGA [14]. The mean time between soft-errors arising on the configuration memory could be extended 1.35-1.89 million times longer than that of current FPGAs.
Moreover, a multi-context scrubbing operation which can simultaneously increase the soft-error and total-ionizing-dose tolerances has been proposed [15]. Always, the serial configuration circuit on FPGAs is firstly down by radiation. Therefore, while current FPGAs cannot treat a permanent failure caused by radiation, RHORGAs can treat a permanent failure by exploiting their robust optical parallel configuration capability [16] because in the optical parallel configuration, each configuration bit becomes independent so that one configuration bit failure does not affect the configuration for the other gate array configuration bits. The optical configuration of RHORGAs is very robust against radiation.
Since RHORGAs can have a number of spare configuration contexts using a different hardware resource, a number of spare configuration contexts are cyclically programmed onto a programmable gate array as the multi-context scrubbing operation. If a configuration context dose not work, another configuration context using a different hardware resource can be used. Therefore, even if a permanent failure happens on a programmable gate array, the programmable gate array can be repaired within tens of nanoseconds by virtue of the multi-context scrubbing operation.
However, although the previously proposed multi-context scrubbing operation could repair circuits themselves on a programmable gate array, it could not repair the current state of sequential circuits. If a flip-flop is suddenly broken by radiation, a state kept in the flip-flop is lost. This means, in the conventional multi-context scrubbing operation, each time a permanent failure occurs on a programmable gate array, all operations must be restarted from the initial condition. Therefore, the conventional multi-context scrubbing operation could not be applied for real-time systems.
Therefore, this paper presents a proposal of the world-first optical multi-context scrubbing method that can maintain the state of a sequential circuit and its gate array operation continuously without any interruption even after a permanent failure suddenly occurs on a sequential circuit or flip-flops by radiation, based on the previous research [17].
2. Multi-context scrubbing operation
2.1 Multi-context scrubbing operation on a triple-modular-redundant system
Up to now, a multi-context scrubbing operation has been proposed [15]. However, the multi-context scrubbing operation has only been demonstrated for combinational circuits. When the multi-context scrubbing method is applied for a sequential circuit without any specific technique, if a D-flip-flop on the sequential circuit is broken by radiation as shown in Fig. 3, although the sequential circuit itself can be recovered by using another flip-flop through the multi-context scrubbing operation, a state stored on the flip-flop is lost. Therefore, all operations on the programmable gate array must be restarted from the initial condition.
Fig. 3. Recovery example from a permanent failure of a D-flip-flop on a sequential circuit. If a spare D-flip-flop can be used, a sequential circuit itself can be recovered by using a multi-context scrubbing operation although the state of the sequential circuit is lost.
However, if a redundant system or a triple-modular-redundant system can be applied for the multi-context scrubbing operation as shown in Fig. 4(a), the state of a sequential circuit can be maintained even after a permanent failure occurs on the sequential circuit. Here, the triple-modular-redundant system shown in Fig. 4(a) is a 2-bit state machine which consists of three state transition logic circuits, three pairs of two D-flip-flops, and three pairs of two majority voting circuits. A circuit diagram of the majority voting circuit is shown in the upper left of Fig. 4 [18]. For example, if a multi-context scrubbing operation is executed on a triple-modular-redundant system, even if a flip-flop on the triple-modular-redundant system is permanently broken by radiation, other flip-flops can maintain the state of the sequential circuit. Therefore, even after a flip-flop is broken permanently, the correct operation can be continuously executed on the triple-modular-redundant system without any interruption as shown in Fig. 4(b). While the correct operation is continuously executed, the triple-modular-redundant system can be repaired from the failure situation shown in Fig. 4(b) to a fixed situation, as shown in Fig. 4(c), that avoids a faulty region and uses another hardware resource. The timing diagram of the multi-context scrubbing operation is shown in Fig. 5. Normally, a certain configuration context C0 is frequently programmed onto a programmable gate array as a scrubbing operation. If a flip-flop is permanently broken by radiation suddenly, as the period ${\# }0$ shown in Fig. 5, so that a certain difference can be detected between the outputs from three modules. At the beginning of the next clock cycle, the multi-context scrubbing system identifies which module is broken by using the failure detection circuits as shown in Fig. 6. Then, a configuration context C1 that never uses the failure hardware resource is programmed onto the programmable gate array for the period ${\# }1$ as a multi-context scrubbing operation. Subsequently, the module including the failed flip-flop is replaced with new one as shown in Fig. 4(c). However, even if the reconfiguration C1 is completed, the replaced flip-flops never hold a current state for the period ${\# }2$. Therefore, more one clock cycle is necessary to restart the triple-modular-redundant operation. As a result, the triple-modular-redundant system becomes a single modular system only for three clock cycles at maximum.
Fig. 5. Timing diagram of a scrubbing operation on the triple modular redundancy of a state machine.
In order to realize the reconfiguration from a configuration context Co to a configuration context C1, in advance, a number of configuration contexts are recorded onto the holographic memory. For example, a 2-bit triple modular redundant state machine consists of three 2-bit state machines as shown in Fig. 4(a) and one 2-bit state machine is used as a spare as shown in Fig. 4(c). Naming the four 2-bit state machines as A, B, C, and D, four configuration contexts of a triple modular-redundant state machine using 2-bit state machines A, B, and C, using 2-bit state machines A, B, and D, using 2-bit state machines A, C, and D, and using 2-bit state machines B, C, and D are recorded in the holographic memory in advance. If a failure occurs on either A, B, C, or D, a configuration context not using the failed 2-bit state machine is selected for reconfiguration.
2.2 Soft-error analysis
Radiation incidence can be analyzed using a Poisson distribution [14,15]. Here, it is assumed that radiation incidence inevitably causes a single event upset. The probability $P$($m$) of $m$ simultaneously occurring incidences in a certain period T is calculable using the following equation as
where $\bar {N}$ represents the average number of incidences for the period. When a system is not redundant, since any radiation incidence causes a soft-error, only the situation that never causes soft-error is P(0), as shown below.On the other hand, the survival probability of a triple modular redundant (TMR) system can be estimated as presented below.
Correct operation probability $P_{TMR}$ of a TMR system is much higher than that $P_{Single}$ of a single module system. For example, assuming that the scrubbing operation period is 1 $\mu s$ and 1 particle is incident to a system at 1 s intervals, for three periods, the soft-error probability $1-P_{TMR}$ of a TMR system is $3.33 \times 10^{-13}$ while the soft-error probability $1-P_{Single}$ of a single module system is $3.3 \times 10^{-7}$. Although soft-error tolerance of the system is decreased while repairing the system, since the optical scrubbing operation period is very short, the soft-error tolerance decrease can be out of consideration.
3. Demonstration of the multi-context scrubbing operation for a 1-bit counter circuit
3.1 Triple-modular-redundant 1-bit counter circuit
For demonstration, a triple modular redundant 1-bit counter circuit was prepared. Each 1-bit counter circuit consists of a majority voting circuit with three inputs, a state transition logic or an inverter, and a flip-flop. Three 1-bit counter circuits construct a triple-modular-redundancy. Moreover, the three triple-modular-redundant 1-bit counter circuits that use a different hardware resource and a partly overlapped hardware resource were prepared. Three configuration contexts corresponding to three triple-modular-redundant 1-bit counter circuit were cyclically programmed onto a programmable gate array as a multi-context scrubbing operation.
3.2 Experimental system
Figure 7 presents a photograph of an optical system that can execute the proposed multi-context scrubbing operation. The optical system consists of a RHORGA-VLSI, three holographic memories (silver photomask film; Unno Giken Co., Ltd.), and three semiconductor lasers (L462P1400MM; Thorlabs, Inc.). The distance between semiconductor lasers and holographic memories was 50 mm. The distance between holographic memories and the RHORGA-VLSI was designed as 100 mm. A photograph of the RHORGA-VLSI chip is portrayed in Fig. 8. Its specifications are presented in Table 1. The power and wavelength of the three semiconductor lasers are, respectively, 1400 mW and 462 nm. Each laser in the laser array corresponds to one configuration context pattern: circuit information can be read out one-by-one by lighting up the laser associated with the targeted holographic memory. By rapid switching of the laser illumination, circuits can be rewritten quickly. The three holographic memories were made using a silver photomask film with 25,400 dpi resolution. Each region of the holographic memory is 10 mm $\times$ 10 mm. After three 1-bit counter circuits using different hardware resources were calculated using a computer [13], the configuration contexts were recorded onto the holographic memory as shown in Fig. 10. By irradiating this holographic memory pattern with a laser, circuit information can be read out as a two-dimensional diffraction pattern that represents a binary pattern of light spots and dark spots. By reading this binary pattern of the diffraction pattern using the multiple photodiodes implemented on the RHORGA-VLSI, the gate array circuits can be configured. Most importantly, this holographic memory has high total-ionizing-dose tolerance: it can sustain a total dose of up to 1 Grad [9].
Fig. 7. Radiation-hardened optically reconfigurable gate array (RHORGA) which can support the multi-context scrubbing operation.
Table 1. Specifications of a RHORGA-VLSI
The RHORGA-VLSI has an island type programmable gate array consisting of logic blocks, switching matrices, and I/O blocks. The logic block includes two D flip-flops (D-FFs) and two four-input look up tables (LUTs). Since each programming point of the programmable gate array is connected to an optical reconfiguration circuit as shown in Fig. 9, the RHORGA-VLSI is optically programmable. In an optical reconfiguration procedure, firstly, electric charge is charged in the junction capacitance of all photodiodes by activating the refresh signal (nRefresh). After electric charge is fully charged in the junction capacitance of all photodiodes , the refresh signal (nRefresh) is negated. Then, a configuration context pattern is generated from a holographic memory by activating a corresponding laser diode and is optically programmed onto photodiodes on the RHORGA-VLSI. At that time, the electric charge on the junction capacitance of photodiodes that receive light is discharged while the electric charge on the junction capacitance of photodiodes that never receive light is maintained. Such binary state is stored on each D-flip-flop by raising the configuration clock signal (CCLK) and then the configuration context is provided to the programmable gate array. A successive optical reconfiguration procedure can be started at the end of the previous reconfiguration procedure. A successive optical reconfiguration preparation by which the refresh signal is activated and then negated, a laser diode is activated, and finally photodiodes receive a configuration context can be executed as a background job while the programmable gate array functions with a previous configuration context. After the next optical reconfiguration preparation is completed, raising the configuration clock signal, the configuration context is quickly changed without any overhead as shown in Fig. 5. The ORGA has been demonstrated as having high radiation tolerance, withstanding a total dose of up to 1.15 Grad [16].
Fig. 10. Three holographic memory patterns. Each holographic memory pattern includes a triple modular redundant 1-bit counter.
3.3 Experiment results
A multi-context scrubbing operation with three configuration contexts was demonstrated using the system described above. The oscilloscope measurement result is shown in Fig. 12. Three configuration contexts for a 1-bit counter circuit could be programmed onto the RHORGA-VLSI within 432 ns, 447 ns, and 1 $\mu s$, respectively. The configuration contexts were programmed onto the RHORGA-VLSI in turn. The counter operation could be executed correctly without any interruption between scrubbing operations. Figure 11 presents photographs of configuration context patterns taken using a CCD camera. The worst-case period of the multi-context scrubbing operation was evaluated as $1 \mu$s. When assuming that 1 radiation is incident to the RHORGA-VLSI during each 1 s interval and that there is no permanent failure, using the $1 \mu$s multi-context scrubbing operation, the soft-error interval of the RHORGA-VLSI can be evaluated as 34.7 days. If a permanent failure occurs on the RHORGA-VLSI, focusing the short period of 1 ms around the failure, the soft-error interval is decreased to about 17 minutes. However, since the probability that a permanent failure occurs is always very low, for example, at least, the failure interval is over 1 day, discussing the period of a day, the soft-error interval can be estimated to be nearly equal to 34.7 days. Therefore, permanent failures never affect the total-soft-error tolerance of the RHORGA-VLSI. The proposed multi-context-scrubbing operation on a triple-modular-redundant system can be applied for real-time systems.
Fig. 11. CCD-captured diffraction patterns generated from corresponding holographic memory patterns.
Fig. 12. Measurement results of the multi-context scrubbing operation with three configuration contexts.
4. Conclusion
This paper has presented a proposal of a multi-context scrubbing method that is applicable for any real-time sequential circuit on a radiation-hardened optically reconfigurable gate array. The scrubbing operation for a 1-bit sequential circuit could be executed within a period of 1 $\mu$s, which is about 100,000 times faster than that for existing FPGAs. Moreover, a system protected by this scrubbing operation can continue to function with no termination even after a flip-flop is permanently destroyed by radiation. Although current system was constructed on an optical test bench, future RHORGAs will be molded from plastic material. At that time, the package size will be decreased to 5 cm by 5cm by 1 cm. As a result, any alignment and stability issues will be perfectly removed.
Funding
Initiatives for Atomic Energy Basic and Generic Strategic Research (JPJA22F22683756); Ministry of Education, Culture, Sports, Science and Technology Grant-in-Aid for Scientific Research(B), (21H03407), Grant-in-Aid for Challenging Research (Pioneering), (22K18415).
Acknowledgments
The VLSI chip in this study was fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Rohm Co. Ltd. and Toppan Printing Co. Ltd.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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