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Abstract
In this work, we demonstrate for the first time a narrow-linewidth III-V-on-Si double laser structure with more than a 110 nm wavelength tuning range realized using micro-transfer printing (µTP) technology. Two types of pre-fabricated III-V semiconductor optical amplifiers (SOAs) with a photoluminescence (PL) peak around 1500 nm and 1550 nm are micro-transfer printed on two silicon laser cavities. The laser cavities are fabricated in imec’s silicon photonics (SiPh) pilot line on 200 mm silicon-on-insulator (SOI) wafers with a 400 nm thick silicon device layer. By combining the outputs of the two laser cavities on chip, wavelength tunability over S+C+L-bands is achieved.
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1. Introduction
Silicon photonics (SiPh) has developed at a rapid rate by leveraging the extremely mature silicon manufacturing ecosystem as a result of decades of CMOS development [1]. In addition to the availability of mature process technology, large wafer sizes of 200 mm or 300 mm [2] make SiPh the leading candidate for high volume production of photonic integrated circuits (PICs) with high uniformity and yield [3]. The high index contrast of the silicon-on-insulator (SOI) platform results in compact low-loss bends in waveguides and extremely compact power splitters, grating couplers, multiplexers, demultiplexers and polarization diversity components [4–7], which makes it possible to have thousand of photonic elements in a PIC.
Since silicon does not provide optical gain, as it is an indirect bandgap material, having integrated light sources and optical amplifiers is still a stumbling block which limits the functionality of PICs on SiPh [8]. Therefore, it is essential for SiPh to be combined with III-V materials [4] as a gain medium, in order to e.g. provide integrated widely tunable lasers to make SiPh’s foothold firm in a wide variety of applications and markets such as coherent optical communication and datacenters [9–14], sensing and spectroscopy [15,16], LiDAR, deep learning and quantum applications [17].
A proper external cavity design can provide both wavelength tunability and linewidth reduction for semiconductor lasers [18,19]. Therefore, there have been great efforts in recent years in assembling a gain chip with a passive SiPh chip as an external cavity [3,20–26]. Although this hybrid approach allows the optimization of the gain chip and external cavity separately, its limited scalibility and critical alignment requirement of each individual assembled laser increases the cost [18].
Various heterogeneous III-V-on-Si integration methods, which enable the integration of extended cavity lasers on a single chip [18,19], have been intensively investigated as well [27]. Heterogeneous integration of III-V semiconductors on SiPh, such as flip-chip integration, wafer-to-wafer/die-to-wafer bonding [28–30], and even hetero-epitaxial growth [31–33] provides a solution to combine the best of both worlds [28].
Although the flip-chip integration comes with the advantage of being able to test the III-V devices in advance, it suffers from limited throughput [34] due to its sequential assembly using active or passive alignment. In contrast, the die-to-wafer bonding approach has the advantage of high throughput, since the unpatterned wafers do not need accurate alignment [34]. However, it also faces some challenges as the SiPh back-end flow needs to be modified and it needs a dedicated III-V process implemented on 200 mm and 300 mm wafers as well. The hetero-epitaxial growth, while allowing for the highest integration density, has drawbacks in terms of III-V material quality [35].
Here, we use micro-transfer-printing ($\mu$TP) [34] for the integration of pre-fabricated InP-based SOAs as the gain section in a SiPh cavity to realize narrow-linewidth widely tunable lasers (WTL). The PICs are fabricated in imec’s SiPh pilot line on 200 mm SOI wafers with a 400 nm thick silicon device layer and a 2 $\mu$m thick buried oxide layer (BOX), including a back-end stack incorporating the heaters and metal tracks. The $\mu$TP process is based on the use of an elastometric poly-dimethylsiloxane (PDMS) stamp to pick-up the pre-fabricated InP-based SOA (which is undercut by selectively etching the release layer) from its native III-V source wafer and to print it on the target substrate, which has recesses in the back-end down to the 3 $\mu$m wide Si-waveguide. A spray-coated divinylsiloxane bisbenzocyclobutene (DVS-BCB) adhesive bonding layer enables a high-yield printing process. The technique allows for high-throughput (massively parallel) and wafer-scale III-V integration while it minimally disrupts the SiPh process flow and does not require singulation and handling of individual III-V chips. Furthermore, $\mu$TP provides the possibility of a dense integration of different non-native components on the SiPh platform [35], which was successfully exploited in the realization of the demonstrated laser in this work.
This paper is organized as follows. We start with explaining the architecture and design of the narrow-linewidth widely tunable extended cavity III-V-on-Si laser in Section 2. In Section 3, the fabrication process flow of III-V SOAs and the $\mu$TP process are presented. The experimental results of the fabricated devices are then provided and discussed in Section 4. Finally, we conclude the paper by providing a summary and a discussion on future directions for further improving the laser performance.
2. Design of the narrow-linewidth widely tunable III-V-on-Si external cavity laser
As depicted in Fig. 1 the widely tunable laser is realized by combining two individual extended laser cavities in a single mode waveguide connecting to a grating coupler as the output of the laser. Each laser has a different SOA gain peak wavelength. The length of the III-V SOAs is 1 mm, including a pair of 180 $\mu$m long adiabatic tapers, with starting width of 4 $\mu$m and end width of 0.6 $\mu$m, for an efficient coupling between the III-V SOA and the underlying Si-waveguide [34]. The adiabatic taper design of the SOA keeps the required alignment accuracy of $\mu$TP within the range of $\pm 1.5$ $\mu$m ($3\sigma$) provided by commercial state-of-the-art micro-transfer-printing tools. An additional pair of adiabatic 50 $\mu$m long Si tapers is used to couple the optical mode between the 3 $\mu$m wide Si-waveguide underneath the III-V SOA and the single-mode rib waveguide.
Fig. 1. Schematic layout of the combined tunable laser cavity design. For simplicity, just one pair of electrical connections to a heater is shown.
A Mach-Zehnder interferometer (MZI) based thermally tunable Sagnac loop mirror is used as an out-coupling mirror, which enables the optimization of out-coupling mirror reflectivity. A thermo-optic phase tuning section is used to tune the cavity modes of the laser. A pair of thermally tunable micro-ring resonators (MRRs) with slightly different radii (27 $\mu$m and 29.3 $\mu$m) is used to form a Vernier filter enabling wavelength selection with a wider effective free spectral range (FSR) [4] resulting in a broader tuning range than each individual ring resonators. The FSR of each ring is about 4 nm and the combined FSR of the Vernier filter is about 55 nm in the envisioned wavelength range.
High Q-factor and being low loss are two essential factors for a narrow-linewidth laser cavity [3,4,18,19]. The Q-factor and the insertion loss (IL) of a ring resonator are highly dependent on the gap between the ring and its bus waveguide [36]. In this work, the ring resonator gap of 300 nm is chosen, while the waveguide loss of the platform is about $1\pm 0.15$ dB/cm. This leads to a loaded Q-factor of about 15000 and IL of about 1.7 dB, which practically balances the high Q-factor and low loss requirement of the narrow-linewidth laser cavity.
3. Device fabrication
3.1 Processing of SOAs on InP substrate
The fabrication of the SOAs, which was carried out by III-V Lab, starts with an InP wafer. The epitaxial layer structure, shown in Fig. 2(a) and detailed in Table 1, is grown by metal-organic vapor-phase epitaxy (MOVPE) with two multi-quantum wells (MQWs) zone variants to achieve laser emissions around 1525 nm and 1575 nm. The 100 nm InP sacrificial layer is then removed by 1 HCl : 3 $\text {H}_{\text {3}}\text {PO}_{\text {4}}$ etching (Fig. 2(b)) to deposit a 300 nm thick Silicon Nitride ($\text {SiN}_{\text {x}}$) by plasma-enhanced chemical vapor deposition (PECVD) at 250$^{\circ }$C (Fig. 2(c)) to use as a hard mask for SOA mesa etching. The hard mask is then patterned using electron beam (e-beam) lithography to define the SOA mesa and III-V adiabatic taper structures. The p-GaInAs, p-GaInAsP, and p-InP layers are etched by inductively coupled plasma (ICP) etching followed by an anisotropic p-InP etching using 1 HCl : 3 $\text {H}_{\text {3}}\text {PO}_{\text {4}}$ for 3 minutes to form the mesa negatively angled side walls (Fig. 2(d)). Another $\text {SiN}_{\text {x}}$ hard mask, which also protects the side walls, is then deposited to use for MQWs patterning by ICP (Fig. 2(e)). Ti/Pt/Au contacts on the n-InP are formed through a lift-off process (Fig. 2(f)). A new layer of $\text {SiN}_{\text {x}}$ is deposited to protect the whole device and also to be used as a new hard mask to define the device island in the n-InP layer (Fig. 2(g)). Next, the GaInAs and AlInAs layers are etched through (Fig. 2(h)) including a hundred nanometers of the InP substrate. Tethers are then defined by $\text {SiN}_{\text {x}}$ deposition and reactive ion etching (RIE) (Fig. 2(i)), which will support the III-V coupons during the selective chemical etching of the release layer and act as anchors for the suspended device. The narrowest part of the tethers is close to the coupon and will break during the micro-transfer-printing, whereas the widest part sits on the InP substrate. As shown in Fig. 2(j) the whole device is then encapsulated with a thick layer of DVS-BCB. The DVS-BCB was then thinned to reach the top of the waveguides and the $\text {SiN}_{\text {x}}$ covering the top of the waveguide was etched before the p-contact is deposited by lift-off (Fig. 2(k)). Next, vias were etched in the DVS-BCB and $\text {SiN}_{\text {x}}$ to reach the n-contacts and a mesa is formed around the coupons to separate single structures from each other and to give access to the release layer (Fig. 2(l)). Figure 3(a) shows a scanning electron microscope (SEM) image with a side-view of a fabricated InP coupon before release etch. Prior to the release etching (Fig. 2(n)) using a $\text {FeCl}_{\text {3}}$ wet-etch, a layer of Ti35E photoresist (PR) is spin-coated to encapsulate devices and at the same time to reinforce the tethers as shown in Fig. 2(m). These coupons, which are 40 $\mu$m wide and 1 mm long, are fabricated in a dense array with a vertical pitch of 70 $\mu$m on the InP substrate (Fig. 3(b)).
Table 1. III-V SOA epitaxial layer stack with two multi-quantum wells (MQWs) zone variants to achieve PL peaks around 1500 nm and 1550 nm. Using these two epi-stacks in this work leads to laser emissions around 1525 nm and 1575 nm.
3.2 Micro-transfer-printing process
Prior to the $\mu$TP a combination of dry-etch (by RIE) and wet-etch (by BHF) was firstly applied to the SiPh chip to remove the back-end stack containing 2 $\mu$m thick silicon dioxide on the Si-waveguide (Fig. 4(a)), to form the recess where the InP-based SOA will be integrated. The locally opened recess is slightly longer and wider than the pre-fabricated III-V SOA. Using about 45 minutes of $\text {SF}_{\text {6}}$-$\text {CF}_{\text {4}}$-$\text {H}_{\text {2}}$ RIE made it possible to stop slightly above the Si waveguide. The process is completed by immersing the structures for about 1 minute in buffered-HF (BHF), where full etching of the oxide layer resulted in exposing the Si-waveguides. Next, a thin DVS-BCB adhesive layer with a thickness of 100 nm was spray-coated (Fig. 4(b)) to enhance the bonding strength between the III-V SOA and the underlying Si-waveguide, followed by a short soft bake at 110$^{\circ }$C. During the spray-coating, DVS-BCB will build up at the edges of the cavity allowing the metallization in the last step to run over the sidewall of the recess, which here is about 4.5 $\mu$m high. Before $\mu$TP, a short soft bake of the spray-coated sample at 150$^{\circ }$C was done to re-flow the DVS-BCB, resulting in a smooth printing process. $\mu$TP of III-V SOAs was done using an X-Celeprint $\mu$TP-100 lab-scale printer, shown in Figs. 4(c)–4(g). Figure 3(b) shows a microscope top-view image of an InP source after $\mu$TP of several coupons. The process continues with an oxygen-plasma etch to remove the PR encapsulation on the printed III-V SOAs and remove spray-coated DVS-BCB on electrical bond pads (Fig. 4(h)). The post-printing processing finishes by electrically connecting the printed SOAs to the SiPh back-end using 1 $\mu$m thick Au, shown in Fig. 4(i). Figure 5 shows a stitched microscope image of the fabricated lasers, having two transfer-printed SOAs, combined in a single output waveguide using a 3 dB-combiner. The SOA printed on the first individual laser (laser 1) has a gain peak around 1525 nm and the SOA on the second individual laser (laser 2) has a gain peak around 1575 nm.
Fig. 5. (a) Stitched microscope image of the combined widely tunable lasers. (b) Micro-transfer printed III-V amplifier in the recess (after final metallization).
4. Characterization
To characterize the combined widely tunable lasers, the sample is placed on a temperature-controlled stage stabilized at 15$^{\circ }$C, as shown in Fig. 6. The output of the lasers is coupled to a single-mode fiber (SMF), which is connected to a 10%/90% optical splitter which guides the light to an optical power meter and an optical spectrum analyzer (OSA). Multiple Keithley 2400 Sourcemeters are used to bias the SOAs and a Keysight Triple Output Power Supply (E36300 series) is used to bias the thermal tuning elements (ring resonators, phase shifters and Sagnac loop mirrors) by using DC probes. Reference waveguides with grating couplers are also fabricated on the same sample (PIC), which went through all the same processes as the laser cavities to calibrate the loss of the mentioned components and calculate the on-chip optical power after the 3 dB-combiner in the single-mode waveguide.
A differential series resistance of about 10 Ω is measured while the laser 1 and 2 are biased at 120 mA. The measured threshold current of the lasers is about 60 mA. Figure 7 shows the wavelength tuning behavior of the combined laser biased at 120 mA. Discrete wavelength tuning is done by thermally tuning one of the micro-rings and phase section of each individual laser, which resulted in a tuning range of 111 nm. Fine-tuning in steps of 100 pm is achieved by thermally tuning both the micro-rings and the phase section of each individual laser, as shown in Fig. 7 over the wavelength range of 1582-1586 nm.
Fig. 7. Wavelength tuning behavior of the combined widely tunable laser with ring gap of 300 nm. (Fine tuning is done in the steps of 100 pm over a range of 4 nm, which is equal to the FSR of one ring.)
Figure 8 shows the laser’s frequency noise power spectral density biased at 120 mA measured using an OEwaves-OE4000 Optical Phase Noise Test System while the lasing wavelength is 1530 nm. The Lorentzian linewidth corresponding to the shown frequency noise spectrum is about 20 kHz. Although linewidth variations are observed over the laser tuning range, the frequency noise spectrum consistently remains below the linewidth threshold mask provided by OIF-400-ZR [37].
Fig. 8. Frequency-noise power spectral density of the widely tunable laser characterized by OE4000 Optical Phase Noise Test System.
5. Conclusion
For the first time, we demonstrate a narrow-linewidth III-V-on-Si dual laser structure with more than 110 nm tuning range by micro-transfer printing pre-fabricated InP-based SOAs on a SiPh platform. Two different SOAs with a gain peak around 1525 nm and 1575 nm are used to provide gain over a wide wavelength range. These coupons, which are 40 $\mu$m wide and 1 mm long, are fabricated in a dense array with a vertical pitch of 70 $\mu$m on the InP substrate. A pair of adiabatic tapers on both sides of the coupon is used for efficient evanescent coupling of the III-V gain waveguide to the Si waveguide. To achieve the phase match condition and thus an efficient mode conversion between the III-V/Si and Si waveguide, thick Si waveguides (400 nm and above) are normally required [14]. In this work, imec’s SiPh platform with 400 nm of Si thickness and 180 nm etch step is used. The SiPh external cavity design resulted in a narrow-linewidth output, over the entire wavelength tuning range, below the frequency noise threshold mask provided by OIF-400-ZR.
Although >400 nm thickness of Si waveguide is normally required for efficient evanescent coupling of the III-V to Si waveguide, we recently realized a widely tunable III-V-on-Si laser with 40 nm tuning range using $\mu$TP on imec’s iSIPP50G platform [35]. iSIPP50G is an imec’s advanced 220 nm SiPh platform [2]. The efficient coupling is provided using a 160 nm poly-Si layer on top of the 220 nm Si waveguide in the coupon printing zone (recess) underneath the III-V SOA.
$\mu$TP allows for high-throughput and wafer-scale III-V integration with minimal disruption to the SiPh process flow and without singulation and handling of individual III-V chips. This work is a stepping stone towards the realization of complex PICs with integrated lasers and semiconductor optical amplifiers for a wide range of applications.
The use of an optical switch instead of the 3 dB-combiner is considered to combine individual laser cavities for future works, in order to avoid 3 dB loss. For coherent communication applications, the next steps are the integration of booster SOAs and a wavelength locking system. These implementations in a future work would provide more optical output power over the wavelength tuning range while meeting the frequency accuracy requirements of various coherent communication applications.
Funding
Horizon 2020 Framework Programme (814276 (ITN-WON), 825453 (CALADAN), 871345 (MedPhab)).
Acknowledgments
The authors would like to thank Liesbet Van Landschoot, Muhammad Muneeb, and Steven Verstuyft for assistance related to fabrication and processing. Emadreza Soltanian thanks Javad Rahimi Vaskasi, Camiel Op de Beeck, Clemens Krückel and Jasper Jans for assistance related to characterization and constructive discussions.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.
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