Abstract

A compact low-loss optical tap technology is critical for the incorporation of optical interconnects into mainstream complementary metal-oxide-semiconductor (CMOS) processes. For this work, an effort has been made to establish an optimal integrated optical tap design in terms of optical loss, bandwidth, economy,and process compatibility with multimetal layer CMOS circuits. A new device,which is based on a variation of the multimode interference effect, has been found to be especially promising. Two-dimensional (2-D) and three-dimensional (3-D) simulation results show low excess optical loss (< 0.1 dB) for the design, and a nominal 40% (2.2 dB) optical coupling into the CMOS circuitry over a wide range of guide to substrate distances. Simulated tap devices are on the order of 15 μm in length. Polymer waveguide materials are targeted for tap fabrication due to planarization properties, low cost, broad index control, and poling abilities for modulation-tuning functions. Low-cost silicon CMOS-based processing makes the new tap technology especially suitable for computer multichip module and board level interconnects, as well as for metro fiber to the home and desk telecommunications applications.

© 2002 IEEE

PDF Article

References

You do not have subscription access to this journal. Citation lists with outbound citation links are available to subscribers only. You may subscribe either as an OSA member, or as an authorized user of your institution.

Contact your librarian or system administrator
or
Login to access OSA Member Subscription

Cited By

You do not have subscription access to this journal. Cited by links are available to subscribers only. You may subscribe either as an OSA member, or as an authorized user of your institution.

Contact your librarian or system administrator
or
Login to access OSA Member Subscription