Abstract

A hardware-based parallel decoding scheme is proposed to address the problems of correctness and efficiency of software decoding for ternary optical computers. Based on the minimal primitive structure of the ternary optical computer, a hardware decoding voltage divider circuit and single-pixel transcoding of operation results are designed. A parallel decoding scheme is designed for the SJ-MSD unconventional adder based on Shen’s theorem and the TW-MSD conventional adder under the degraded design theory, and a corresponding addressing scheme is proposed for the access of decoding results. After comprehensive consideration, the decoding scheme is finally selected as the time-sharing combination. The experiments show that the parallel decoding scheme of the ternary optical computer is practical and feasible.

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