Abstract

Design technology co-optimization (DTCO) is a potential approach to tackle the escalating expenses and complexities associated with pitch scaling. This strategy offers a promising solution by minimizing the required design dimensions and mitigating the pitch scaling trend. It is worth noting that lithography has played a significant role in dimensional scaling over time. This paper proposes a DTCO flow to reduce the impact of the process variation (PV) band and edge placement error (EPE). First, we performed the digital back-end design of the high-performance processor and got the test layout; second, we executed timing analysis on the test layout to get the critical path net that affects the chip performance; third, we proposed the timing-aware optimized optical proximity correction (OPC) method to optimize the PV band and EPE by adjusting the weights of critical path net merit points, optimizing the generation of the sub-resolution assistant feature, giving tighter EPE specs for merit points on the critical path net, and placing denser merit points as well as denser breakpoints for the critical path net to obtain greater freedom in the OPC process. Finally, it is verified that our proposed DTCO process can significantly reduce the EPE and lead to a slight decrease in the PV band of the chip while maintaining the same process windows.

© 2023 Optica Publishing Group

Inverse lithography physics-informed deep neural level set for mask optimization

Xing-Yu Ma and Shaogang Hao
Appl. Opt. 62(33) 8769-8779 (2023)

Exposure latitude aware source and mask optimization for extreme ultraviolet lithography

Lulu Zou, Yiyu Sun, Pengzhi Wei, Miao Yuan, Zhaoxuan Li, Lihui Liu, and Yanqiu Li
Appl. Opt. 60(30) 9404-9410 (2021)

Lithography-defect-driven source-mask optimization solution for full-chip optical proximity correction

Austin Peng, Stephen D. Hsu, Rafael C. Howell, and Qinglin Li
Appl. Opt. 60(3) 616-620 (2021)

Process optimization of line patterns in extreme ultraviolet lithography using machine learning and a simulated annealing algorithm

Rongbo Zhao, Ziyu Hu, Xiaolin Wang, Peipei Tao, Yimeng Wang, Tianqi Liu, Yayi Wei, Hong Xu, and Xiangming He
Appl. Opt. 62(11) 2892-2898 (2023)

Retargeting of forbidden-dense-alternate structures for lithography capability improvement in advanced nodes

Jianfang He, Lisong Dong, Lijun Zhao, Yayi Wei, and Tianchun Ye
Appl. Opt. 57(27) 7811-7817 (2018)