Table 1
Operation Pairs Controlled by C and
Control Input | Logical Operations |
---|
C | or | and | A +
| A
|
| A | B | false |
| nor | nand | ĀB | Ā + B | xor | Ā |
| true |
Table 2
Grouping for the Output of the Adder–Subtracter
Output | Sharing | Nonsharing |
---|
S or D | (2, 3) | (5, 8) |
C′ | (4, 8) | (6, 7) |
B | (2, 3), (4, 8) | |
Table 3
Output Locations of the or Operations
Input Pixels | OR Output Pixel | Output |
---|
(1, 1), (1, 2); | (1, 2) | S or D |
(1, 1), (2, 1); | (2, 1) | B |
(2, 1), (2, 2); | (3, 2) | C′ |
Table 4
Operations Obtained by C and
Control Input | Logical Operations |
---|
C | or | and | A +
| A
|
| A | B | false |
C | nor | nand | ĀB | Ā + B | xor | Ā |
| true |
Table 5
Outputs with Corresponding Input Conditions
Logical Operation | Input Conditions | Logical Operation | Input Conditions |
---|
and | (8) | nand | (1, 3, 5) |
or | (4, 6, 8) | nor | (1) |
| (2, 8) | xor | (3, 5) |
A | (6, 8) | Ā | (1, 3) |
B | (4, 8) |
| (1, 5) |
A
| (6) | Ā + B | (1, 3, 7) |
A +
| (2, 6, 8) | ĀB | (3) |
false | (none of the even minterms) | true | (1, 3, 5, 7) |
Table 6
Locations for Obtaining Outputs from the Output Overlap Pixel
Input Pixel | Output Pixel | Output |
---|
(1, 1) | (1, 1) | ĀB |
(1, 1), (1, 2) | (1, 2) | Sum, xor,
|
(1,2), (1,3) | (1,3) | and,
|
(1, 3) | (1, 4) | nor |
(1, 1), (1, 2), (2, 1), (2, 2) | (2, 2) | A +
|
(1, 2), (1, 3), (2, 2), (2, 3) | (2, 3) | true, A |
(1, 3), (2, 3) | (2, 4) | nand, false |
(2, 1) | (3, 1) | B |
(2, 1), (2, 2) | (3, 2) | or |
(2, 2), (2, 3) | (3, 3) | Ā + B, A
|
(2, 3) | (3, 4) | Ā |
Table I
Truth Table for the Arithmetic Section of the ALU
Input Conditions | INPUT | OUTPUT |
---|
|
|
---|
A | B | C | S | D | C′ | B |
---|
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
2 | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
3 | 0 | 1 | 0 | 1 | 1 | 0 | 1 |
4 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
5 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
6 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
7 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
8 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Table II
Partitioned Truth Table for Arithmetic Section of the ALU
Output Operations | Input Conditions | Primry Input | Primay Code | Secondary Input C | Output |
---|
|
---|
A | B |
---|
Sum (S) | 1 | 0 | 0 | V | 1 | 1 |
Difference (D) | 2 | 1 | 1 | H | 1 | 1 |
| 3 | 0 | 1 | V | 0 | 1 |
| 4 | 1 | 0 | H | 0 | 1 |
Carry-out (C′) | 1 | 0 | 0 | V | X | 0 |
| 2 | 1 | 1 | H | X | 1 |
| 3 | 0 | 1 | V | 1 | 1 |
| 4 | 1 | 0 | H | 1 | 1 |
Borrow-out (B) | 1 | 0 | 0 | V | 1 | 1 |
| 2 | 1 | 1 | H | 1 | 1 |
| 3 | 0 | 1 | V | X | 1 |
| 4 | 1 | 0 | H | X | 0 |
Table III
Truth Table for 16 Logical Operations of Two Binary Variables
Input Conditions | Input | Output |
---|
|
|
---|
A | B | and | nand | or | nor | xor |
| A | Ā | B |
| A
| Ā + B | A +
| ĀB | true | false |
---|
1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
2 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
3 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
4 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 |
Table IV
Truth Table for the and and nand Operations with Control Input C
Input Conditions | Primary Inputs | Primary Code | Control Input C | Output |
---|
|
---|
A | B |
---|
and |
1 | 0 | 0 | V | 1 | 0 |
2 | 1 | 1 | H | 1 | 1 |
3 | 0 | 1 | V | 1 | 0 |
4 | 1 | 0 | H | 1 | 0 |
nand |
5 | 0 | 0 | V | 0 | 1 |
6 | 1 | 1 | H | 0 | 0 |
7 | 0 | 1 | V | 0 | 1 |
8 | 1 | 0 | H | 0 | 1 |
Table V
Table for Nonzero Outputs of and and nand Operations
Input Conditions | Primary Inputs | Primary Code | Control Input C | Output |
---|
|
---|
A | B |
---|
5 | 0 | 0 | V | 0 | 1 |
2 | 1 | 1 | H | 1 | 1 |
7 | 0 | 1 | V | 0 | 1 |
8 | 1 | 0 | H | 0 | 1 |
Table VI
Table for Nonzero Outputs of A and Ā Operations
Input Conditions | Primary Inputs | Primary Code | Control Input C | Output |
---|
|
---|
A | B |
---|
5 | 0 | 0 | V | 0 | 1 |
2 | 1 | 1 | H | 1 | 1 |
7 | 0 | 1 | V | 0 | 1 |
4 | 1 | 0 | H | 1 | 1 |
Table VII
Input Encoding of Control Input for Different Logical Operations
| Code |
---|
|
|
---|
Logical Operations | C |
|
---|
or | nor |
|
|
and | nand |
|
|
| xor |
|
|
A | Ā |
|
|
B |
|
|
|
A +
| ĀB |
|
|
A
| Ā + B |
|
|
false | true |
|
|
Table VIII
Truth Table for 16 Logical Operations of Two Binary Variables, Including the Control Input
Input Conditions | Input | Output |
---|
|
|
---|
A | B | C | or | and |
| A +
| A
| A | B | false |
---|
2 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
6 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 |
8 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |
| | | | nor | nand | xor | ĀB | A + B | Ā | B | true |
1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 |
3 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
5 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |
7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
Table IX
Input Pixel Encodings for Parallel ALU
| Pixel Code |
---|
|
|
---|
Input | 1 | 0 |
---|
A |
|
|
B |
|
|
C |
|
|