1. Introduction

Vertical-injection GaN-based light-emitting diodes (vertical LEDs) are regarded as one of the most promising platform for the realization of high-efficiency and high-power lighting engines due to their figure of merit such as excellent current injection, enhanced heat dissipation, improved reliability against electrostatic discharge, scalability of chip dimension, true Lambertian emission, and simple packaging process [1–4]. Despite these advantages, the vertical LEDs suffer from relatively poor process yields over lateral LEDs, which are caused by complicated fabrication procedure involving physical separation of sapphire substrates, so-called laser lift-off (LLO) process [2,3]. For example, the LLO process was shown to generate cracks in GaN epitaxial films. The N-polar GaN surface exposed after LLO process was also shown to have different physical properties as compared to those of conventional Ga-polar one due to opposite crystallographic direction and hence polarization field. As a consequence, the characteristics of etching or metal contacts on N-polar GaN were reported to be quite different from those on Ga-polar surfaces [5–8], which may degrade LED performance and process yields. In addition, although the vertical LEDs show better current spreading over the lateral LEDs, the current injection was sensitively dependent on the configuration of p- and n-electrodes [9]. These design and fabrication process issues still need to be addressed for better process yield and superior LED performances. However, studies on this subject are very limited.

In this article, we investigated the critical unit processes for the fabrication of noble vertical LEDs including reflective p-electrode, dry and wet etching of N-polar GaN surfaces and their influences on the process yield and performance characteristics of vertical LEDs. In addition, the chip design utilizing current blocking layer (CBL) and branched n-electrodes and its scaling effect on the LED performances were investigated.

2. Process of vertical LEDs

2.1 Fabrication procedure and characterization method of vertical LEDs

The epilayer structure of LED wafers studied here consists of the sapphire substrate, ~3.0 μm-thick undoped GaN, ~3.0 μm-thick n-GaN, 5 periods of 10 nm-thick GaN/3 nm-thick InGaN multiple quantum well, a p-GaN/p-AlGaN electron blocking layer, and 70 nm-thick p-GaN. For an electrical isolation, a square mesa with side dimensions of 300 μm was dry-etched by an inductively-coupled plasma reactive ion etching (ICPRIE) system and 400 nm-thick SiO₂ films were then deposited using plasma enhanced chemical vapor deposition. Using an e-beam evaporator, 200 nm-thick AgCu was deposited on mesa as a reflective p-electrode and thermally annealed at 400 °C for 1 min in N₂: O₂ = 1:1 ambient [10]. To protect AgCu surface, a 400 nm-thick TiW was deposited on the p-electrodes by dc sputtering method. A Ni(30 nm)/Au(600 nm) layer was e-beam evaporated on the entire wafer as a conductive seed layer, on which 40 μm-thick Ni was electroplated. Using a KrF excimer laser (248 nm), a LLO process was then performed to separate the sapphire substrate from the GaN films. The separated GaN surface was wet-etched to remove Ga droplets using HCl solution and subsequently dry-etched by ~3.5 μm to expose the n-layer, on which a Cr(200 nm)/Au(500 nm) was deposited as an n-electrode. To form textured surfaces, LEDs were dipped into a 2.2 M-KOH solution [11]. Electrical and optical characteristics of the LEDs were measured using an on-wafer testing configuration, comprising a parameter analyzer and calibrated optical spectrometer mounted above the wafers. The peak wavelength of LEDs measured at 20 mA was about 460 nm.

2.2 Adhesion issues of Ag-based reflective p-electrodes

Ag-based metal contacts were generally employed as reflective p-electrodes in vertical LEDs due to their best reflectivity among metals and excellent Ohmic formation upon thermal annealing [10,12,13]. However, Ag was shown to suffer from the poor adhesion caused by the compressive stress formed in films. Accordingly, the compressive stress accumulated in Ag film relaxes upon thermal annealing through the generation of interfacial voids accompanied by the surface agglomeration, leading to a poor adhesion as well as to degradations in both contact resistance and reflectivity. Our group showed that the incorporation of alloying element such as Cu (or Ni) into Ag can prevent the generation of interfacial voids as shown in Fig. 1a , resulting in a better reflectivity, thermal stability, adhesion, and surface smoothness [10,13]. In this respect, the vertical LEDs were fabricated with AgCu reflective p-electrodes.

 

Fig. 1 Ag-based electrode and its influence on LLO process. (a) Transmission electron microscopy (TEM) z-contrast image of AgCu p-electrodes. (b) The optical microscopic images of LEDs fabricated with Ag after LLO process.

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To understand the effect of p-electrodes on the LLO-process yield, two types of vertical LEDs were fabricated with AgCu and Ag. Figure 1b shows the optical microscopic images of LEDs fabricated with Ag after LLO process. It is shown that chips contain cracks and the GaN films are even delaminated as shown by stereoscopic black images. In contrast, the LEDs fabricated with AgCu revealed no cracks or delamination (not shown). This indicates that the use of proper p-electrodes with good adhesion is essential to build high-yield vertical process.

2.3 Dry etching of undoped GaN with N-polar surfaces

After LLO process, the dry etching is essentially needed to remove undoped GaN layer, on which n-electrode is formed. The dry etching of conventional Ga-polar GaN surfaces has been investigated by a number of groups [14]. However, studies on dry etching of N-polar GaN are rare. Our group [6] showed that the etch rate of N-polar GaN is 10-20% faster than that of Ga-polar one across entire Cl₂ gas ratio (under 300 W-ICP/150 W-rf power, gas flow rate of 50 sccm, and 3mTorr conditions) as shown in Fig. 2a . This could be due to the more defective nature of N-polar GaN since it is close to the buffer layer and a relatively abundant nitrogen fractions at N-polar surfaces (note that the volative element is beneficial in terms of dry etching). The inset of Fig. 2a shows the typical 1 μm × 1 μm Ga-polar and N-polar surface images obtained from atomic force microscopy (AFM) after dry etching, exhibiting the rms roughness of 8 and 25 Å, respectively. Note that the N-polar surface is rougher than Ga-polar one presumably due to Ga-droplet induced masking effects or faster etching rate at N-polar surfaces.

 

Fig. 2 Dry etching of N-polar GaN. (a) The dry etching rate of Ga-polar and N-polar GaN as a function of %Cl₂. (b) SEM images of N-polar surfaces degraded after dry etching.

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Dry etching was found to induce substantial surface roughness if the electroplated metal was exposed in plasma gas. Figure 2b shows the scanning electron microscopy (SEM) images of chips degraded after dry etching. An analysis of roughened GaN surface by energy dispersive spectroscopy (EDS) revealed existence of chemical species comprising Ni and Au (not shown), which are major constituents in electroplated Ni or seed layer. This indicates that the electroplated metal contaminated the N-polar surfaces and subsequently induced surface roughness as a result of masking effect. The degraded surface was also found to deteriorate n-type Ohmic properties (not shown). These results suggest that the electroplated metal layer should be entirely protected (for instance by photoresist) prior to exposure in Cl₂/Ar plasma. The surface degradation could be further suppressed by sufficient cooling down of wafers.

2.4 Wet etching of N-polar GaN surfaces

One of the most important problems hindering the fabrication of high-efficiency LEDs is the occurrence of trapped light within a high refractive-index GaN [1]. For vertical LEDs, this issue is still critical, but the substantial enhancement in light extraction can be obtained using crystallographic wet etching of N-polar n-type GaN as shown in the upper inset of Fig. 3a . The hexagonal cones with {10-1-1} facets and inclined angle of 28° were formed under wet-etching condition of 2.2 M KOH for 2.5 hr at room temperature [5]. The cone structures have 500-700 nm in base, 470-660 nm in height, and 5.3 × 10⁸ cm⁻² in density. Note that, using this structure, the light extraction efficiency could be enhanced by a factor of 2.03 as compared to the non-etched flat surfaces as shown in Fig. 3a. Figure 3a shows the light extraction efficiency of LEDs as a function of cone density calculated using optical ray-tracing method [11]. The lower inset of Fig. 3a shows schematic structures used in the calculation.

 

Fig. 3 Wet etching of N-polar surface and its influence on light extraction. (a) The light extraction efficiency of vertical LEDs as a function of cone density. The upper and lower inset shows the SEM images of KOH-etched N-polar GaN and the schematic used for ray-tracing simulation, respectively. (b) TEM images of vertical chips (mesa sidewall) after KOH wet etching.

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To implement the KOH wet etching for LED fabrications, it is important to check its unexpected influence on the chips, namely, the degradation in reflective p-electrodes (AgCu and TiW), electroplated Ni layer, SiO₂ passivation layer, and n-electrodes (Ti, Cr, and Al). After wet etching, no structural and physical differences were observed in AgCu, TiW, Ni, Au, and SiO₂. Figure 3b shows the TEM images of vertical LED after wet etching. It is shown that the SiO₂ passivation layer remained unchanged. On the other hand, Al was completely removed after wet etching. In addition, the surface oxide was observed in wet-etched Ti and Cr. In this regard, the Cr/Au scheme was finally used as n-electrodes, while the Al (the most conventional n-electrodes in lateral LED) was not employed.

Figure 4a shows the electroluminescence (EL) spectra of vertical LEDs before and after wet etching. Note that the interference fringes disappear upon wet etching as a result of random scattering of guided mode. In addition, the EL intensity improves by a factor of 2, which is in good agreement with theoretical calculations. To investigate process capability, the distribution of optical output power and the forward voltage (measured at 20 mA) were plotted before and after wet etching as shown in Fig. 4b and 4c. Note that the wet etching induces pronounced fluctuations in optical outputs and forward voltages, which may degrade process yields. Furthermore, the forward voltage was slightly increased after wet etching, which is due to the reduced n-layer thickness acting as current channel. This indicates that careful process design and controllable texturing process (for instance photolithographic patterning and dry etching [15]) should be taken into consideration for the fabrication of noble vertical LEDs.

 

Fig. 4 The LED performance before and after wet etching. (a) The EL spectra, (b) the optical output power, and (c) the forward voltages of vertical LEDs before and after wet etching.

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3. Design of vertical LEDs

To maximize the current injection and light output, it is important to best optimize the chip design, namely, the complete suppression of dead current flowing underneath of n-electrodes and the efficient spreading of current through n-GaN layer [9], as shown in Fig. 5a . To study this subject, we fabricated five different types of vertical LEDs according to the uses of SiO₂ CBL and branched n-electrodes as shown in Fig. 5b. In addition, the chip dimension was varied from 300 to 500 μm to investigate the scaling effects. Note that the LED A has both the CBL and branched n-electrodes. For LED B, the CBL is only used underneath of circular n-electrode. The LED C has CBL but no branched n-electrodes, while the LED D is vice versa. The LED E has neither CBL nor n-branched electrodes.

 

Fig. 5 The chip design of vertical LEDs using CBL and branched n-electrodes. (a) The schematic cross-sectional view of LEDs having CBL. (b) The schematic top-views of LED A-E (c) The forward voltage, (d) optical output power, and (e) the power efficiency of LED A-E.

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Figure 5c and 5d shows the forward voltages (V _f) and the optical output power (P) of LEDs as a function of chip design. Note that the LED A, B, and D have relatively lower forward voltages, indicating that the adoption of branched n-electrodes is effective in current spreading. In addition, the LED A, B, and C have relatively higher output power, indicating that the CBL is critical in enhancing the light output by suppressing the dead current. Accordingly, the plotted power efficiency (η) defined as η = P/IV _f, where I is the driving current (20 mA) showed that the LED A is the best design optimized in 300 μm scale (Fig. 5e). Interestingly, however, for LEDs with 400 and 500 μm dimensions, the LED B exhibited slightly higher power efficiency than that of LED A. These results suggest that the considerate design optimization be considered for the fabrication of high-efficiency vertical LEDs.

4. Conclusion

The process and design issues for the fabrication of noble GaN-based vertical LEDs were investigated. The adhesion property of reflective p-electrode affected the process yield of LLO. The dry etching rate of N-polar GaN was found to be 10-20% faster than that of Ga-polar GaN. Specifically, the exposure of electroplated metal into plasma gas caused the substantial surface degradation. The wet etching of N-polar GaN induced textured surfaces with cone structures, resulting in an enhancement of light extraction by a factor of 2 by both experimentally and theoretically. However, the wet etching induced fluctuations in optical output power and forward voltages. The design optimization using branched n-electrodes and CBL structures were found to be very effective in enhancing the power efficiency of vertical LEDs.