Abstract

Free-space optical interconnection (FSOI) of integrated circuits, called smart pixels, show great potential for efficient implementation of high-performance parallel computing, switching and signal processing systems [1]. Several FSOI technologies are now under development and prototype FSOI systems have been demonstrated. However, there has been relatively little published work that describes integrated circuit design for large-scale smart pixel ICs with over 100,000 transistors and thousands of optical I/O channels operating at 100Mbps/channel or higher data rates. Such a detailed design study is the objective of this paper. We focus on a specific problem of designing a large-scale optically-accessed SRAM. The work described in this paper builds on our earlier effort that produced a two kilobit 21,000 transistor hybrid CMOS-SEED photonic page buffer IC [2]. The 64 optical I/O channels on this IC were optically tested at 50Mbps/channel optical data throughput; corresponding to an aggregate optical data I/O bandwidth of 3.2Gbps in a 1mm² chip area.

© 1997 Optical Society of America