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Digital Optoelectronic Processor Array Architectures for Vector-Matrix Multiplication

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Abstract

High speed computation of the product of a vector and a matrix is desirable for problems in neural networks, signal processing, artificial intelligence and many other applications. If the number of elements in the vector is N, and the number in the matrix is N2, then a serial computer requires a time which grows at least as N2 to complete the computation. Many processing elements (PE's) can be combined to form a processor array in order to decrease the computation time. Electrically connected processor arrays are effective for locally connected parallel processing networks[1], A linear mesh can be used to perform the multiplication in time proportional to N [2], However to compute the product in shorter time, more complicated schemes with non local connection lengths are required. For such networks, the interconnections themselves are often responsible for a large percentage of the computation time, power dissipation and silicon area. Optically interconnected processor arrays can be employed to reduce this communication bottleneck. Previous work has shown that optical interconnections have advantages in terms of power dissipation and communication bandwidth for sufficiently long interconnection paths[3], and in terms of area for sufficiently complex connection networks[4].

© 1989 Optical Society of America

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