Abstract
The latest generation of coherent pluggable modules impose strict power limits on the coherent ASIC. The development process for a low-power coherent ASIC designed in a 7nm FINFET process is described. The ASIC enables pluggable coherent modules with energy efficiency of 40-60pJ/bit for various 400G DWDM applications.
© 2022 The Author(s)
PDF Article | Presentation Video