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Conferences > OFC > 2017 > W4G > W4G.3

A Chip-Scale Heterodyne Optical Phase-Locked Loop with Low-Power Consumption

Arda Simsek, Shamsul Arafin, Seong-Kyun Kim, Gordon Morrison, Leif A. Johansson, Milan Mashanovitch, Larry A. Coldren, and Mark J. Rodwell

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Abstract

A chip-scale heterodyne optical phase-locked loop, consuming only 1.3 W of electrical power, with a maximum offset locking frequency of 17.4 GHz is demonstrated. The InP-based photonic integrated receiver circuit consumes only 166 mW.

© 2017 Optical Society of America

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