Abstract

The miniaturization of integrated circuit elements by scaling in very large scale integrated circuits (VLSI) has created a great deal of interest in the timing skew associated with transmitting signals via circuit lines to remote locations on a chip. As device sizes decrease and chip sizes increase with technological advances, the speed of the circuits on a VLSI chip becomes limited by signal transmission delays rather than device switching delays. Of particular interest is the clock signal that allows the system operations to be timed synchronously with one another. Parasitic transmission line capacitance and resistance over varying path lengths for this widely distributed signal cause a skew in its arrival time at different locations on the chip. In our approach, the 3-D nature of imaging optics is utilized to distribute the clock signal to multiple detectors. The chip is divided into functional areas within which transmission line delays are negligible, and the clock signal is distributed optically to a detector in each region. In this manner, interregional skew effects are reduced to the variation of switching speeds of the detectors and amplifiers in different functional areas, and intraregional skew effects are negligible. In addition, the division of the chip into smaller areas allows the capacitive load for each clock driver to be orders of magnitude less than that typical of chip-wide clock drivers. SPICE circuit simulations show that this difference in loading allows the optical clock driver transition delay to be less than the chip-wide electronic clock driver transition delay by a factor of 4. Design and fabrication of test circuits to measure transition delay for the optical circuit and photocurrent leakage effects in 4-µm CMOS technology are now in progress.

© 1985 Optical Society of America