Abstract

We experimentally demonstrate extraction of silicon waveguide geometry with subnanometer accuracy using optical measurements. Effective and group indices of silicon-on-insulator (SOI) waveguides are extracted from the optical measurements. An accurate model linking the geometry of an SOI waveguide to its effective and group indices is used to extract the linewidths and thicknesses within respective errors of 0.37 and 0.26 nm on a die fabricated by IMEC multiproject wafer services. A detailed analysis of the setting of the bounds for the effective and group indices is presented to get the right extraction with improved accuracy.

© 2018 Chinese Laser Press

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References

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    [Crossref]
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    [Crossref]
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    [Crossref]
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    [Crossref]
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    [Crossref]
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    [Crossref]
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    [Crossref]
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    [Crossref]
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    [Crossref]
  20. M. Fiers, T. Van Vaerenbergh, J. Dambre, and P. Bienstman, “CAPHE: time-domain and frequency-domain modeling of nonlinear optical components,” in Advanced Photonics Congress, OSA Technical Digest (Optical Society of America, 2012), paper IM2B.3.
  21. D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
    [Crossref]

2018 (1)

W. Bogaerts and L. Chrostowski, “Silicon photonics circuit design: methods, tools and challenges,” Laser Photon. Rev. 12, 1700237 (2018).
[Crossref]

2017 (1)

2016 (1)

2015 (4)

2014 (3)

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 8202008 (2014).
[Crossref]

2013 (2)

2012 (1)

2011 (1)

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

2010 (2)

W. A. Zortman, D. C. Trotter, and M. R. Watts, “Silicon photonics manufacturing,” Opt. Express 18, 23598–23607 (2010).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

Absil, P.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in IEEE International Conference on Group IV Photonics GFP (2011), pp. 71–73.

Ayotte, N.

N. Ayotte, A. D. Simard, and S. Larochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photon. Technol. Lett. 27, 755–758 (2015).
[Crossref]

Baets, R.

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

Beausoleil, R. G.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Bienstman, P.

S. Dwivedi, A. Ruocco, M. Vanslembrouck, T. Spuesens, P. Bienstman, P. Dumon, T. Van Vaerenbergh, and W. Bogaerts, “Experimental extraction of effective refractive index and thermo-optic coefficients of silicon-on-insulator waveguides using interferometers,” J. Lightwave Technol. 33, 4471–4477 (2015).
[Crossref]

M. Fiers, T. Van Vaerenbergh, J. Dambre, and P. Bienstman, “CAPHE: time-domain and frequency-domain modeling of nonlinear optical components,” in Advanced Photonics Congress, OSA Technical Digest (Optical Society of America, 2012), paper IM2B.3.

Bogaerts, W.

W. Bogaerts and L. Chrostowski, “Silicon photonics circuit design: methods, tools and challenges,” Laser Photon. Rev. 12, 1700237 (2018).
[Crossref]

Y. Xing, D. Spina, A. Li, T. Dhaene, and W. Bogaerts, “Stochastic collocation for device-level variability analysis in integrated photonics,” Photon. Res. 4, 93–100 (2016).
[Crossref]

S. Dwivedi, A. Ruocco, M. Vanslembrouck, T. Spuesens, P. Bienstman, P. Dumon, T. Van Vaerenbergh, and W. Bogaerts, “Experimental extraction of effective refractive index and thermo-optic coefficients of silicon-on-insulator waveguides using interferometers,” J. Lightwave Technol. 33, 4471–4477 (2015).
[Crossref]

S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photon. Technol. Lett. 27, 871–874 (2015).
[Crossref]

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 8202008 (2014).
[Crossref]

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

S. Pathak, D. Van Thourhout, and W. Bogaerts, “Design trade-offs for silicon-on-insulator-based AWGs for (de)multiplexer applications,” Opt. Lett. 38, 2961–2964 (2013).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in IEEE International Conference on Group IV Photonics GFP (2011), pp. 71–73.

A. Ribeiro, S. Dwivedi, and W. Bogaerts, “A thermally tunable but athermal silicon MZI filter,” in 18th European Conference on Integrated Optics 2016 (ECIO), Warsaw, Poland (2016).

Chen, X.

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

X. Chen, M. Mohamed, Z. Li, L. Shang, and A. R. Mickelson, “Process variation in silicon photonic devices,” Appl. Opt. 52, 7638–7647 (2013).
[Crossref]

Chrostowski, L.

D’heer, H.

S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photon. Technol. Lett. 27, 871–874 (2015).
[Crossref]

Dambre, J.

M. Fiers, T. Van Vaerenbergh, J. Dambre, and P. Bienstman, “CAPHE: time-domain and frequency-domain modeling of nonlinear optical components,” in Advanced Photonics Congress, OSA Technical Digest (Optical Society of America, 2012), paper IM2B.3.

Daniel, L.

Delvaux, C.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Dhaene, T.

Dumon, P.

S. Dwivedi, A. Ruocco, M. Vanslembrouck, T. Spuesens, P. Bienstman, P. Dumon, T. Van Vaerenbergh, and W. Bogaerts, “Experimental extraction of effective refractive index and thermo-optic coefficients of silicon-on-insulator waveguides using interferometers,” J. Lightwave Technol. 33, 4471–4477 (2015).
[Crossref]

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 8202008 (2014).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

Dwivedi, S.

S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photon. Technol. Lett. 27, 871–874 (2015).
[Crossref]

S. Dwivedi, A. Ruocco, M. Vanslembrouck, T. Spuesens, P. Bienstman, P. Dumon, T. Van Vaerenbergh, and W. Bogaerts, “Experimental extraction of effective refractive index and thermo-optic coefficients of silicon-on-insulator waveguides using interferometers,” J. Lightwave Technol. 33, 4471–4477 (2015).
[Crossref]

A. Ribeiro, S. Dwivedi, and W. Bogaerts, “A thermally tunable but athermal silicon MZI filter,” in 18th European Conference on Integrated Optics 2016 (ECIO), Warsaw, Poland (2016).

Faraon, A.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Fattal, D.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Fernandez, L.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in IEEE International Conference on Group IV Photonics GFP (2011), pp. 71–73.

Fiers, M.

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 8202008 (2014).
[Crossref]

M. Fiers, T. Van Vaerenbergh, J. Dambre, and P. Bienstman, “CAPHE: time-domain and frequency-domain modeling of nonlinear optical components,” in Advanced Photonics Congress, OSA Technical Digest (Optical Society of America, 2012), paper IM2B.3.

Fiorentino, M.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Flueckiger, J.

Grist, S.

Hautala, J.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in IEEE International Conference on Group IV Photonics GFP (2011), pp. 71–73.

Horikawa, T.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

Jaeger, N. A. F.

Jeong, S.-H.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

Jhoja, J.

Keyvaninia, S.

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

Kinoshita, K.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

Klein, J.

Larochelle, S.

N. Ayotte, A. D. Simard, and S. Larochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photon. Technol. Lett. 27, 755–758 (2015).
[Crossref]

Lepage, G.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Li, A.

Li, Z.

Liu, A.

Locorotondo, S.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Lu, Z.

Marzouk, Y.

Mashanovich, G. Z.

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

Melloni, A.

Mickelson, A. R.

Milenin, A.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Mogami, T.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

Mohamed, M.

Murdoch, G.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Nedeljkovic, M.

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

Ong, P.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Pathak, S.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

S. Pathak, D. Van Thourhout, and W. Bogaerts, “Design trade-offs for silicon-on-insulator-based AWGs for (de)multiplexer applications,” Opt. Lett. 38, 2961–2964 (2013).
[Crossref]

Peng, Z.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Pond, J.

Reed, G. T.

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

Ribeiro, A.

A. Ribeiro, S. Dwivedi, and W. Bogaerts, “A thermally tunable but athermal silicon MZI filter,” in 18th European Conference on Integrated Optics 2016 (ECIO), Warsaw, Poland (2016).

Rosseel, E.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in IEEE International Conference on Group IV Photonics GFP (2011), pp. 71–73.

Ruocco, A.

Santori, C.

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

Schmid, J. H.

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

Selvaraja, S. K.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

S. K. Selvaraja, “Wafer-Scale Fabrication Technology for Silicon Photonic Integrated Circuits,” Ph.D. thesis (University of Ghent, 2011).

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in IEEE International Conference on Group IV Photonics GFP (2011), pp. 71–73.

Shang, L.

Shi, W.

Shiina, A.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

Shimura, D.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

Simard, A. D.

N. Ayotte, A. D. Simard, and S. Larochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photon. Technol. Lett. 27, 755–758 (2015).
[Crossref]

Sobu, Y.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

Spina, D.

Spuesens, T.

Sterckx, G.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Su, Z.

Tabat, M.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in IEEE International Conference on Group IV Photonics GFP (2011), pp. 71–73.

Takahashi, H.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

Thomson, D. J.

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

Tokushima, M.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

Trotter, D. C.

Ushida, J.

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

Van Campenhout, J.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Van Thourhout, D.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

S. Pathak, D. Van Thourhout, and W. Bogaerts, “Design trade-offs for silicon-on-insulator-based AWGs for (de)multiplexer applications,” Opt. Lett. 38, 2961–2964 (2013).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

Van Vaerenbergh, T.

S. Dwivedi, A. Ruocco, M. Vanslembrouck, T. Spuesens, P. Bienstman, P. Dumon, T. Van Vaerenbergh, and W. Bogaerts, “Experimental extraction of effective refractive index and thermo-optic coefficients of silicon-on-insulator waveguides using interferometers,” J. Lightwave Technol. 33, 4471–4477 (2015).
[Crossref]

M. Fiers, T. Van Vaerenbergh, J. Dambre, and P. Bienstman, “CAPHE: time-domain and frequency-domain modeling of nonlinear optical components,” in Advanced Photonics Congress, OSA Technical Digest (Optical Society of America, 2012), paper IM2B.3.

Vanslembrouck, M.

Wang, X.

Watts, M. R.

Weng, T.-W.

Winroth, G.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Xie, W.

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Xing, Y.

Xu, D.-X.

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

Yun, H.

Zhang, Z.

Zortman, W. A.

Appl. Opt. (1)

IEEE J. Sel. Top. Quantum Electron. (3)

D.-X. Xu, J. H. Schmid, G. T. Reed, G. Z. Mashanovich, D. J. Thomson, M. Nedeljkovic, X. Chen, D. Van Thourhout, S. Keyvaninia, and S. K. Selvaraja, “Silicon photonic integration platform—have we found the sweet spot?” IEEE J. Sel. Top. Quantum Electron. 20, 8100217 (2014).
[Crossref]

W. Bogaerts, M. Fiers, and P. Dumon, “Design challenges in silicon photonics,” IEEE J. Sel. Top. Quantum Electron. 20, 8202008 (2014).
[Crossref]

S. K. Selvaraja, W. Bogaerts, P. Dumon, D. Van Thourhout, and R. Baets, “Subnanometer linewidth uniformity in silicon nanophotonic waveguide devices using CMOS fabrication technology,” IEEE J. Sel. Top. Quantum Electron. 16, 316–324 (2010).
[Crossref]

IEEE Photon. Technol. Lett. (2)

N. Ayotte, A. D. Simard, and S. Larochelle, “Long integrated Bragg gratings for SOI wafer metrology,” IEEE Photon. Technol. Lett. 27, 755–758 (2015).
[Crossref]

S. Dwivedi, H. D’heer, and W. Bogaerts, “Maximizing fabrication and thermal tolerances of all-silicon FIR wavelength filters,” IEEE Photon. Technol. Lett. 27, 871–874 (2015).
[Crossref]

J. Lightwave Technol. (1)

Laser Photon. Rev. (1)

W. Bogaerts and L. Chrostowski, “Silicon photonics circuit design: methods, tools and challenges,” Laser Photon. Rev. 12, 1700237 (2018).
[Crossref]

Opt. Express (4)

Opt. Lett. (1)

Photon. Res. (1)

Proc. SPIE (2)

R. G. Beausoleil, A. Faraon, D. Fattal, M. Fiorentino, Z. Peng, and C. Santori, “Devices and architectures for large-scale integrated silicon photonics circuits,” Proc. SPIE 7942, 794204 (2011).
[Crossref]

S. K. Selvaraja, G. Winroth, S. Locorotondo, G. Murdoch, A. Milenin, C. Delvaux, P. Ong, S. Pathak, W. Xie, G. Sterckx, G. Lepage, D. Van Thourhout, W. Bogaerts, J. Van Campenhout, and P. Absil, “193  nm immersion lithography for high-performance silicon photonic circuits,” Proc. SPIE 9052, 90520F (2014).
[Crossref]

Other (5)

M. Fiers, T. Van Vaerenbergh, J. Dambre, and P. Bienstman, “CAPHE: time-domain and frequency-domain modeling of nonlinear optical components,” in Advanced Photonics Congress, OSA Technical Digest (Optical Society of America, 2012), paper IM2B.3.

S. K. Selvaraja, E. Rosseel, L. Fernandez, M. Tabat, W. Bogaerts, J. Hautala, and P. Absil, “SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device,” in IEEE International Conference on Group IV Photonics GFP (2011), pp. 71–73.

S. K. Selvaraja, “Wafer-Scale Fabrication Technology for Silicon Photonic Integrated Circuits,” Ph.D. thesis (University of Ghent, 2011).

A. Ribeiro, S. Dwivedi, and W. Bogaerts, “A thermally tunable but athermal silicon MZI filter,” in 18th European Conference on Integrated Optics 2016 (ECIO), Warsaw, Poland (2016).

T. Horikawa, D. Shimura, H. Takahashi, J. Ushida, Y. Sobu, A. Shiina, M. Tokushima, S.-H. Jeong, K. Kinoshita, and T. Mogami, “Extraction of SOI thickness deviation based on resonant wavelength analysis for silicon photonics devices,” in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (IEEE, 2017), vol. 10, pp. 1–3.

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Figures (11)

Fig. 1.
Fig. 1. Work flow of extracting behavior parameters and fabricated geometry using optical measurements.
Fig. 2.
Fig. 2. (a) Cross-section schematic of an oxide-clad SOI strip waveguide with a 85° sidewall angle; (b) width and thickness grid of strip waveguides; (c) effective and group indices of strip waveguides on the geometry grid using the COMSOL FEM simulation, and the first-, the second-, or the third-order polynomial mapping model.
Fig. 3.
Fig. 3. Error contour plot of the proposed third-order polynomial model where w ranges from 440 to 500 nm and thickness ranges from 195 to 235 nm. Left, width extraction error; right, thickness extraction error.
Fig. 4.
Fig. 4. (a) Layout of the MZI under test. (b) Circuit schematic of the MZI.
Fig. 5.
Fig. 5. We removed the GC envelope using a reference GC near the DUT. Fabrication variation caused the measured spectrum after GC removal to be far from ideal (as shown by the spectrum simulated by the circuit model), as ideally the peaks in the spectrum should have the same amplitude. After GC removal, we fitted the measured spectrum with the circuit model (Fig. 4), not including the GC. Red solid curve, measured transmission spectrum after removing the GC envelope using a reference GC. Blue dotted curve, fitted spectrum using the circuit model. Left, the low-order MZI. Right, the high-order MZI.
Fig. 6.
Fig. 6. This figure shows the measured transmission spectrum (red solid curve) and fitted spectrum (blue dotted curve) using the circuit model including the polynomial GC model. Also, valleys of the spectrum (green cross) are found by the peak detection method. Left, the low-order MZI. Right, the high-order MZI.
Fig. 7.
Fig. 7. Bounds of the extraction. (a) The bound of width and thickness. (b) Rectangle bound [11] parallelogram, reduced bounds by linear transformation of geometry bounds. (c) Rectangle bounds cannot separate three groups of solutions (red, blue, and green circles). The parallelogram cleanly isolates the correct solutions (blue circles).
Fig. 8.
Fig. 8. Top left, low-order and high-order MZIs we used for geometry extraction. Bottom left, locations of two devices on a die. Right, locations of dies on the wafer. Red grid indicates dies on the wafer. The black circle is the boundary of the wafer.
Fig. 9.
Fig. 9. Extracted neff and ng of the high-order MZI. Left, die (X=0, Y=0); right, die (X=2, Y=2).
Fig. 10.
Fig. 10. x and y coordinates give the locations of the MZIs on two dies. Blue solid dot, extracted value. Green grid, fitted map of extracted values using a bivariate polynomial. (a) Extracted width map of die (X=0, Y=0) (in the center of the wafer). (b) Extracted thickness map of die (X=0, Y=0). (c) Extracted width map of die (X=2, Y=2) (near the edge of the wafer). (d) Extracted thickness map of die (X=2, Y=2).
Fig. 11.
Fig. 11. We extracted the linewidth and thickness on the same device over 21 dies on the wafer. Top left, systematic linewidth variation; bottom left, random linewidth variation; top right, systematic thickness variation; bottom right, random thickness variation.

Tables (4)

Tables Icon

Table 1. Error of Polynomial Models

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Table 2. Comparison between the Peak Detection Method and the Curve Fitting Methoda

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Table 3. Fitting Error versus Interference Order

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Table 4. Statistical Results for the Manufacturing Variations of a 200 mm Wafer Fabricated through a 193 nm DUV Lithography Process

Equations (23)

Equations on this page are rendered with MathJax. Learn more.

w=p0+Σi=1npeineffi+Σj=1npgjngj+Σj=1,i=1m,npegijneffingj,
t=q0+Σi=1nqeineffi+Σj=1nqgjngj+Σj=1,i=1m,nqegijneffingj,
m=neff,0ΔLλres,
FSR=λres2ngΔL,
neff,0ΔLλ=m,(neff,0Δneff/2)ΔLλ>m0.5,(neff,0+Δneff/2)ΔLλ<m+0.5.
m<neff,0Δneff.
ΔL<λΔneff.
neff=neff0+neffw(ww0)+nefft(tt0),ng=ng0+ngw(ww0)+ngt(tt0).
neff1=neff0+neffw(w1w0)+nefft(t1t0),
neff2=neff0+neffw(w2w0)+nefft(t2t0),
ng1=ng0+ngw(w2w0)+ngt(t1t0),
ng2=ng0+ngw(w1w0)+ngt(t2t0),
Δneff,rectangle=neff2neff1=neffwΔw+nefftΔt,
Δneff,parallelogram=(neffwngtngw+nefft)Δt,when  ngtΔt<ngwΔw,
Δneff,parallelogram=(neffwngwnefftngt)Δw,when  ngtΔt>ngwΔw.
Δneff,rectangleΔneff,parallelogram=aΔwΔt+b,
a=neffwneffwngt/ngw+nefft,b=nefftneffwngt/ngw+nefft.
variationtotal=variationinter-die+variationlocation-dependent+variationlocal.
Δneff,total=neffwΔwtotal+nefftΔttotal.
Δneff,local=(neffwngtngw+nefft)Δtlocal.
Δneff,total=neffwΔwtotal+nefftΔttotal=0.002055×40  nm+0.003916×20  nm=0.16.
Δneff,intra-die=(neffwngtngw+nefft)Δtintra-die=0.0074×2=0.0148,
Errorw=0.31+0.06=0.37  nm,Errort=0.18+0.08=0.26  nm.

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