In this study, we report the enhanced light extraction efficiency of light emitting diode (LED) devices by employing multi-chip arrayed LED structures. We analyze the optoelectronic property of multi-chip arrayed LED structures with 16, 36 and 64 LED chips in the same 1 × 1 mm2 device as well as 2 × 2 and 3 × 3 mm2 devices. When compared with a conventional large area single-chip LED structure with the same device size, the multi-chip arrayed LED structures generally exhibit enhanced light extraction efficiency and electrical efficiency owing to the reduced current crowding effect. The effect of chip and device size on the LED performance is discussed.
© 2015 Optical Society of America
In recent years, high power light emitting diodes (LEDs) based on GaN have been intensively researched for their applications in solid state lighting, outdoor decoration, and back lighting in liquid-crystal display [1,2]. In order to make high efficiency LEDs with increasing output power, large LED chip size and much higher injection current are required. However, the large area LED devices have the following problems that degrade LED performances. When the size of LED chips increases, the light emitted from an active layer in an LED is confined within the LED chip owing to the total internal reflection caused by the difference of refractive indices between GaN and air. In particular the moving distance of light within the chip is relatively long in the large LED chip and the intensity of light from LED device inevitably decreases [3,4]. More importantly, the current crowding effect is signified in large LED chips as the current injected into the active layer from the electrode grid spreads non-uniformly throughout the chip, which produces poor chip power and reliability as well as efficiency droop [5–14].
In order to enhance the LED performances by solving the current crowding effect, various approaches have been attempted. The current crowding effect can be reduced by decrease of electrode grid (geometric pattern for electrodes) interval but the degradation of light output power is also inevitable as the increased area of electrodes that reflects light back into the chip . Indium tin oxide (ITO) as highly transparent and conductive p-electrode can be applied to that effect but only for the relatively smaller LED chips . In the case of vertical LED , fabrication process has disadvantages, such as, high cost process and complicated process including wafer bonding.
In this study, we report on the enhanced LED performances by employing multi-chip arrayed LED device structures. The LED devices with 16, 36 and 64 LED chips in the same sized device (1 × 1 mm2) as well as the conventional large-sized one-chip LED device are fabricated and compared. The effects of the number of chips (chip size) and device size of the LED devices on the LED performances are studied both theoretically and experimentally. Also, LEDs with 2 × 2 and 3 × 3 mm2 device sizes were also fabricated and analyzed for further confirmation of the results. These multi-chip device structures also can be applied in various GaN-based devices, such as GaN based solar cell, sensor, and electronic device.
2. Experimental details
The LED epi wafersstudied in this work consist of a p-GaN (0.25 μm, p = 4 × 1017 cm−3), a 5-period InGaN multiple-quantum-well (MQW), n-GaN (1.5 μm, n = 1 × 1018 cm−3) and undoped GaN/sapphire substrates. Using these wafers, we fabricated InGaN/GaN MQW blue LEDs of single and multi-chip arrayed LED devices with conventional planar ITO transparent p-contacts. In order to achieve Ohmic contact for the p-GaN layer, the p-contact ITO electrode layer (3/400 nm thick) was deposited onto p-GaN surfaces by e-beam evaporation and was rapidly annealed at 600 °C in O2 ambient for 1 minute. For an n-type contact, we partially etched the surfaces of the grown LED samples until the n-type GaN layer was exposed. Then, a Ti/Au (50/200 nm) layer as the n-type electrode was deposited by e-beam evaporation. SiO2 insulating layers were deposited on the surfaces of single and multi-chip arrayed LED by plasma-enhanced chemical vapor deposition. Then, a small part of SiO2 layer on ITO p-electrode was etched by BOE solution to form pad electrodes. In order to maximize light emission area, a Cr/Au (50/200 nm) bonding pad on surface of the opened ITO p-electrode and SiO2 layer were deposited by e-beam evaporation as a dual structure electrode (bonding pad electrode/SiO2/n-electrode) in multi-chip arrayed LEDs.
Individual LED chip of multi-chip arrayed LED structures was connected by a Cr/Au bonding pad electrode for effective current injection to each chip. The fabrication process and device structure were schematically presented in Fig. 1(a) and 1(b), respectively. A reference LED is consisted of one chip with an area of 1 × 1 mm2 and multi-chip arrayed LEDs were divided into 4 × 4 (chip size 220 × 220 μm2), 6 × 6 (140 × 140 μm2) and 8 × 8 (100 × 100 μm2) separate chips without any additional process to fabricate multichip LEDs, as shown in Fig. 2(a).In order to analyze the effect of arrayed LED devices for larger sized devices, we also fabricated LED devices with areas of 2 × 2 mm2 and 3 × 3 mm2 (see Fig. 2(b) and 2(c)), which have generally been disregarded due to the significant current crowding effect.
Current–voltage (I–V) measurements of LEDs were carried out using a parameter analyzer (KEITHELY-2400 sourcemeter) and light output–current (L–I) characteristics were measured by Ocean optics-USB4000.
3. Results and Discussion
3.1. Electrical and electroluminescence (EL) characteristics
We compared I-V characteristics of 1 × 1 mm2, 2 × 2 mm2 and 3 × 3 mm2 LED devices as shown in Fig. 3. Figure 3(a) summarizes the dependence of number of chips on I-V characteristics of the 1 × 1 mm2 LED device. It shows that the series resistance decreases as the chip size (number of chips in a device) decreases (increases). This can be explained by the fact that the decrease in individual chip size results in the shortened carrier migration length and the enlarged contact area of bond electrodes . Still, there is no significant improvement in the series resistance when the number of chips in a device increases from 36 to 64, which indicates that the current migration length in a short chip may not be a main factor to further reduce the series resistance.
Figure 3(b) and 3(c) display the I-V characteristics of the larger LED devices with areas of 2 × 2 and 3 × 3 mm2, respectively. Expectedly, the reduction in series resistance in the multi-chip arrayed LED devices (16 chips in the 2 × 2 mm2 LED device and 36 chips in the 3 × 3 mm2 LED device) compared to the reference single-chip LED devices is larger than the results of the 1 × 1 mm2. But, the leakage current in the largest LED device is observed in particular as indicated by an arrow in Fig. 3(b).
Then, we compared electroluminescence (EL) spectra of the samples as compiled in Fig. 4.In the case of 1 × 1 mm2 LED devices, the device with 16 chips produces the ~25% brighter power (in terms of EL peak intensity) than the reference (single-chip) device as shown in Fig. 4(a). We also compared the EL integrated intensity values of the samples and observed the similar trend with a slightly lower proportion (~20%). The light output powers of the devices with 36 and 64 chips are also on par with the power of the single-chip device. Based on the observations, it should be noted that the further chip size optimization, which needs the proper understandings of the current migration length that is dependent on the intrinsic optical property of GaN layers, is necessary to produce better output power. Significant improvement in EL intensity was also found in the case of larger sized multi-chip arrayed LED devices with areas of 2 × 2and 3 × 3 mm2 compared with the single-chip device as shown in Fig. 4(b) and 4(c). We observed that the LED devices with lower series resistance produced shorter wavelength EL peaks, which can be attributed to the temperature dependence of bandgap .
3.2. Electrical and EL characteristics considering active light emitting area
It was shown that the multi-chip arrayed LED device structures exhibit generally higher EL intensity than the conventional single-chip LED device. However, the formation of multiple chips in the same sized LED device inevitably reduce actual light emitting area on the surface that results from the consumed space for chip-separating region and additional electrode. Therefore, we considered the actual active area of LEDsin analysis of LED performances in order to properly compare LED performances of the single-chip and multi-chip LED structures. The “active area” was defined as the light emitting top surface area except the etched area between chips and the area covered by electrodes on top of the LED devices. The active areas and ratios of multi-chip arrayed LED devices with various numbers of chips are summarized and compared with the single-chip 1 × 1, 2 × 2 and 3 × 3 mm2 devices in Table 1.The area ratio of single-chip device is set to be 100%.
After we obtained the active areas and area ratios, we compared the actual current density as a function of voltage of the samples as shown in Fig. 5.When compared the I-V results shown in Fig. 3, the decrease in the operation current density of multi-chip arrayed LED structures is more pronounced for all 1 × 1, 2 × 2 and 3 × 3 mm2 LED devices. In particular, 1 × 1 mm2 LED devices with multiple chips exhibit the dramatic decreases in current density owing to the reduced current crowding effect. Also, the leakage current effect is much alleviated in the larger size 3 × 3 mm2 LED device. These observations prove the advantages of multi-chip structures in terms of electrical property.
In particular, considering the similar EL output powers of 36-chip and 64-chip 1 × 1 mm2 devices (Fig. 4) that have the active areas of only 51.6% and 36.6% of the reference device, it can be concluded that the output power efficiency per active area of multi-chip devices is much higher than the single-chip device. Comprehensive comparisons of the EL output power per active area as a function of input current of all the samples are all summarized in Fig. 6.It should be noted that the LED devices with higher number of chips emit much more lights. Especially, the 64-chip 1 × 1 mm2 LED devices produces more than 2 times higher output per active area than the single-chip 1 × 1 mm2 LED device.Similar trends can also be found in the larger sized 2 × 2 and 3 × 3 mm2 LED devices. This also corroborates the enhanced LED performances of multi-chip structures.
3.3. Efficiency droop
As already mentioned, high power LEDsgenerally suffer the efficiency droop [20,21] with high input current. Therefore, let us move on to theoretical analysis of the effect of chip and device sizes on efficiency droop, normalized efficiency taking into account active region factor in each LED was calculated using the Eq. (1)  and compared.
The calculated normalized external quantum efficiency (EQE) values of the 1 × 1 mm2 LED devices are plotted in Fig. 7.From the evolution of the normalized EQE as a function of current density, it is evident that the efficiency droop effect especially in the region of high input current density is much alleviated as we incorporate more chips in the same size LED device. Almost ideally reduced efficiency droop was demonstrated in the 64-chip 1 × 1 mm2 LED chips . In other words, when the chip size is reduced, the efficiency is maintained even with the increasing input current density, which is also owing to the reduced current crowding effect.
Based on these observations with and without taking into account active area, it can be concluded that the multi-chip arrayed LED structures with further optimization of the number of chips (chip size) even without increasing the device size are very promising to produce large area high power LED devices.
In conclusion, we report the improvement in light output power of LED devices by employing multi-chip arrayed LED structures. We analyzed the optoelectronic property of multi-chip arrayed LED structures with 16, 36 and 64 LED separate chips in the same 1 × 1 mm2 device as well as 2 × 2 and 3 × 3 mm2 devices. The current density (current/area) as a function of voltage and EL output power density (power/area) are significantly improved in multi-chip arrayed LED structures compared to the single-chip LED devices. Especially, the 64-chip 1 × 1 mm2 LED device produces more than 2 times higher EL output power density than the conventional single-chip 1 × 1 mm2 LED device. Also, the analysis of normalized EQE as a function of input current density indicates that the multi-chip arrayed LED devices exhibit reduced efficiency droop effect, which results from the reduced current crowd effect in small chips. Therefore, we conclude that the multi-chip arrayed LED structures with further optimization of the number of chips (chip size) are very promising to realize high power and efficiency LED devices even without exclusively increasing the device size.
The authors are grateful for the support of the Industrial Strategic technology development program, 10041878, Development of WPE 75% LED device process and standard evaluation technology funded by the Ministry of Knowledge Economy (MKE, Korea) and by a Research Program (NRF-2013R1A1A2012113) through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology, Republic of Korea.
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