Drain currents as functions of the gate voltages for the thin-film transistors (TFTs) showed that their output currents had slight differential variations in the saturation region just as the output currents of the etch stopper TFTs did. The maximum difference in the threshold voltages for the In-Ga-Zn-O (a-IGZO) TFTs was as small as approximately 0.57 V. The color gamut of organic light-emitting devices (OLEDs) embedded with TFTs with a coplanar structure satisfied the digital cinema initiatives of 99%. Furthermore, the image density of large-size OLEDs embedded with TFTs with a coplanar structure was significantly enhanced in comparison with that of OLEDs embedded with conventional TFTs.
© 2018 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
Recently, organic light-emitting devices (OLEDs) have been extensively used in promising applications, such as mobile phones, laptop computers, monitors, televisions, car displays, light sources, and public displays [1, 2]. OLEDs have emerged as excellent candidates for next-generation displays, having progressively replaced liquid crystal displays (LCDs) in high-resolution display systems, because OLEDs have self-luminous pixels that overcome the disadvantage of LCDs, which have thick, heavy, back light units (BLUs). OLEDS are thinner and have lighter weight, a wider viewing angle, and a much higher contrast ratio in comparison with LCDs [3, 4].
Much research has been focused on optimizing thin-film transistors (TFTs) based on semiconductor materials as a way to enhance the performances of large-size OLEDs [5,6]. Among the various amorphous-oxide materials, amorphous In-Ga-Zn-O (a-IGZO) thin films have been predominantly considered due to their having significant advantages, such as compatibility with the amorphous silicon process in large-area mass production, high mobility, and both short- and long-range uniformity [7, 8]. Demands for high-performance, high-resolution, and large-size OLEDs have been dramatically increasing with increasing requirements for high-quality image density. Although several inherent problems limit the ability to achieve ultrahigh image density from a large-size OLED, if such an image density were to be achieved using a large-size OLED, that would play an important role in making large-size display systems more practical .
Amorphous silicon TFTs (a-Si TFTs) with a high uniformity have been extensively utilized in the fabrication of large-size LCDs. However, the low mobility and the large threshold voltage (Vth) shift of a-Si TFTs make their use as reliable backplanes for OLEDs difficult . Low-temperature poly-silicon (LTPS) TFTs, which have superior characteristics including high mobility and high stability, are currently being used for small-size OLEDs . However, the use of LTPS TFTs with poor uniformity in large-size OLEDs is difficult unless an additional complicated compensation pixel is included, but the inclusion of such a pixel would decrease the yield rate of mass production . To the contrary, IGZO TFTs can be conveniently manufactured using the existing amorphous Si TFT process line. Even though some investigations on the device performances of conventional TFTs used in displays have been conducted [13–16], studies on the achievement of ultra-high-image-density (UHID) large-size OLEDs containing a-IGZO TFTs with a coplanar structure have not yet been performed.
This paper presents data demonstrating the achievement of an UHID from large-size OLEDs based on a-IGZO TFTs with a coplanar structure. The a-IGZO TFTs with a coplanar were fabricated so as to enhance their uniformity and reliability. Drain currents were measured as functions of the gate voltages for the a-IGZO TFTs to investigate the uniformity of their threshold voltages. Drain currents were also measured as functions of the drain voltages to investigate the saturation characteristics of the currents for the TFTs. Moreover, the drain currents for TFTs that had been subjected to a voltage bias or a current stress were measured as functions of the gate voltages to investigate their current fluctuations and stabilities. Finally, the performance of large-size OLEDs embedded with TFTs with a coplanar structure in producing UHID was investigated.
2. Experimental details
The detailed structure of the etch-stopper-layer (ESL)-type TFTs with a double gate formed by placing gates on the top and the bottom regions of the active layer is described elsewhere . The ESL is necessary to protect the active film against the introduction of contaminants, which might deteriorate the reliability of oxide TFTs, so that a TFT with high performance can be achieved [18–22]. The TFTs with the ESL structure generate large parasitic capacitances between the gates and the drain/source metals.
TFTs with a coplanar structure were fabricated to overcome the drawbacks of the ESL-type TFTs and to satisfy image-density requirements for potential applications in large-size OLEDs. A cross-sectional view of such a self-aligned thin-film transistor with a coplanar structure containing a top gate is shown in Fig. 1. Novel technologies that were adopted for use in this fabrication process included the fabrication of top gate TFTs without overlap between metals, selective metallization of the active layer in the source/drain regions, and the formation of a light shield layer. First, the active layer of the a-IGZO film was formed by using a direct-current sputtering method, after which it was patterned by using a wet-etching method. The gate dielectric materials were formed by using plasma-enhanced chemical-vapor deposition, followed by the growth of a bilayer of MoTi and Cu as a gate electrode. After the gate electrode had been etched in a wet-bath, the gate insulator was dry-etched by using a photoresist of the gate pattern. The concentration of oxygen vacancies in the plasma-treated area was much larger than that in the non-treated area. Oxygen vacancies were easily generated near the surface of the a-IGZO region due to the plasma treatment and were later filled with oxygen from the environment during annealing or the formation of the SiO2 layer. The plasma-treated a-IGZO surface on the source/drain region was formed by using dry etching. The sheet resistance of the a-IGZO on the source/drain region was decreased. The parasitic capacitance of the TFT was dramatically reduced by adopting a top gate TFT and a self-aligned conductive active layer in the source and drain regions. TFTs with a highly conductive a-IGZO film are necessary if the contact resistance is to be reduced and the current flow enhanced [23, 24]. Because the superfluous capacitance of the TFTs interrupts the effective operation of large-size OLEDs and has an adverse impact on their performance, a coplanar structure and an optimized heat process were adapted to improve the reliability of the TFTs [25, 26].
The reliability of the values of the Vth for the TFTs was characterized by using both an in-line probe station and an automatic sensing method. Test element groups (TEGs) with transistors at many sites on the glass substrates were monitored by using an in-line probe station. Additionally, the values of the Vth were determined for the TFTs for all pixels inside the UHID panel by using a real-time automatic Vth sensing method.
3. Results and discussion
Figure 1 shows the cross-sectional view of a self-aligned thin-film transistor with a coplanar structure containing a top gate.
The active layers in the coplanar TFTs, except for the gate mask, were exposed to plasma treatments, resulting in the formation of a highly conductive region. The results from Rutherford backscattering spectrometry performed on the plasma-treated active layer demonstrated that the amount of oxygen at the surface of the active layer was larger than that in the bulk. The detailed results of the Rutherford backscattering spectrometry measurements on the plasma-treated active layer in the coplanar TFTs are described elsewhere . Unlike TFTs with a bottom gate structure, the TFTs with a top gate structure were exposed to light that had been transmitted through the glass substrate. The light shield layer was moderately designed to reduce the negative bias temperature illumination stress. The drain current of the TFTs was observed to increase due to a decrease in the drain-induced barrier lowering. Moreover, coplanar TFTs capped with a light shield layer are considered to be superior candidates for use as TFTs with a backplane structure for enhancing the image density of OLEDs. While the reliability of the TFTs with an ESL structure is better than that of the TFTs with a coplanar structure, which is due to the existence of the ESL protecting the active channel layer [28, 29], the parasitic capacitance of the TFTs with an ESL structure is larger than that of the TFTs with a coplanar structure due to the existence of the overlapping area. Furthermore, the photomask number of the coplanar TFTs is smaller than that of the ESL-type TFTs, resulting in a simpler process.
Figure 2 shows that the uniformities of ∆Vth, which is the difference between the maximum and the minimum values of the Vth for a TFT fabricated on a 2500 mm × 2200 mm glass, were 0.57 and 0.55 V as determined by using the in-line probe station and the automatic Vth sensing method, respectively. This improvement in the uniformity of the Vth for the coplanar TFTs, as compared to that of the ESL TFTs, was achieved via the optimization process.
Figure 3 shows the drain current as a function of the drain-source voltage (Vds) for various values of the gate-source (Vgs) voltage ranging from 5 to 20 V. The variation in the output drain current for the TFTs at Vds = 10 V can be characterized by using the differential dIds/dVds. The value of that differential in the saturation region for coplanar TFTs with a light shield is almost the same as its value in that region for etch stopper TFTs, indicating that the output current of the OLEDs is not significantly affected by variations in the drain-source voltage.
The shifts in the values of Vth for the TFTs were measured under a positive bias temperature stress (PBTS) and under a current stress (CS). Both of these electrical stresses were applied to the TFTs at 60°С using Vgs = + 30 V, Vds = 0 V, and a constant current. The shift in the value of Vth under the PBTS was 0.07 V after 1 h, as shown in Fig. 4(a), whereas the shift in that value under the CS was 0.03 V after 10 h, as shown in Fig. 4(b). Because the device characteristics of coplanar TFTs vary only slightly during long-time operation, under applied voltages, and exposure to environmental temperatures, such TFTs can be used in large-size OLEDs. The uniformity of the current applied to the TFTs in OLEDs is particularly important if reliable outputs from the OLEDs are to be achieved.
Figure 5 shows a cross-sectional view of a large-size OLED embedded with coplanar oxide TFTs fabricated on a 2500 × 2200 mm2 glass substrate. The large-size OLED fabricated on 0.5 t glass, which acts as a bottom emission-type display, consists of coplanar-type TFTs, a white OLED (WOLED) with white, red, green, and blue color layers, and the metal encapsulation. Because the emission region of an OLED increases with decreasing size of the TFT, a coplanar TFT with a smaller size would be useful if promising applications in large-size OLEDs are to be realized.
The characteristics of the white OLEDs are summarized in Table 1. The luminance efficiency of the OLEDs at an operating voltage of 11.6 V was 85.0 cd/A. The Commission Internationale de l'Eclairage (CIE) coordinates of the OLEDs are (0.287, 0.310), indicative of a white color, and the dependence of the color shift on the area is only 0.011. The device characteristics of a 55-inch UHID OLED embedded with TFTs with a coplanar structure for practical mass production are summarized in Table 2. One pixel was designed to contain one white, one red, one green, and one blue sub-pixel and to have an average aperture ratio of 30% and a peak luminance of 500 cd/m2, thus demonstrating the achievement of an UHID large-size OLED. Although a 55-inch full high-definition OLED panel can be designed using conventional TFTs, 55-inch ultra-high-definition (UHD) panels cannot, which is the reason TFTs with a coplanar structure should be used for the fabrication of UHID large-size OLEDs.
Figure 6(a) shows that the maximum luminance of the large-size OLED is 500 nits, indicative of a UHID large-size OLED. As Fig. 6(b) shows, the color gamut of the fabricated OLED satisfies the requirements of the digital cinema initiatives (DCI) of 99%.
4. Summary and conclusions
The top gate, the self-aligned metallization of the active layer as in the source/drain regions, and the light shield layer of the TFTs were selected so as to enhance the image density of the OLEDs. The a-IGZO oxide TFTs with a coplanar structure on glass substrates showed maximum Vth differences of 0.57 V in the TEG transistors and of 0.55 V in the active-area transistors, indicative of their excellent uniformity. The values of the Vth for the TFTs with a coplanar structure after having applied a PBTS for 1 h and a CS for 10 h were slightly shifted to 0.07 and 0.03 V, respectively, indicative of their stability. The maximum luminance of the OLEDs embedded with TFTs with a coplanar structure was as large as 500 nits, and their color gamut exhibited a DCI of 99%, indicative of the achievement of large-size UHID OLEDs. The CIE coordinates of the OLEDs were (0.287, 0.310), indicative of a white color, and the dependence of the color shift on the area was only 0.011. Moreover, the luminance efficiency of the white OLEDs embedded with TFTs with a coplanar structure at an operating voltage of 11.6 V was 85.0 cd/A. Thus, the present observations provide good motivation for envisioning the use of UHID large-size OLEDs embedded with TFTs with a coplanar structure in UHID large-size OLED televisions.
National Research Foundation of Korea (2016R1A2A1A05005502).
This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2016R1A2A1A05005502).
References and links
1. X. Luan, J. Liu, Q. Pei, G. C. Bazan, and H. Li, “Gate-tunable electron injection based organic light-emitting diodes for low-cost and low-voltage active matrix displays,” ACS Appl. Mater. Interfaces 9(20), 16750–16755 (2017). [CrossRef] [PubMed]
2. Z. A. Page, B. Narupai, C. W. Pester, R. Bou Zerdan, A. Sokolov, D. S. Laitar, S. Mukhopadhyay, S. Sprague, A. J. McGrath, J. W. Kramer, P. Trefonas, and C. J. Hawker, “Novel strategy for photopatterning emissive polymer brushes for organic light emitting diode applications,” ACS Cent. Sci. 3(6), 654–661 (2017). [CrossRef] [PubMed]
3. H.-J. Kim, M.-H. Shin, J.-S. Kim, S.-E. Kim, and Y.-J. Kim, “High efficient OLED displays prepared with the air-gapped bridges on quantum dot patterns for optical recycling,” Sci. Rep. 7, 43063 (2017). [CrossRef] [PubMed]
4. J. Smith, A. Shah, Y. K. Lee, B. O’Brien, D. Kullman, A. Sridharan, J. Muthuswamy, and J. B. Christen, “Optogenetic neurostimulation of auricular vagus using flexible OLED display technology to treat chronic inflammatory disease and mental health disorders,” Electron. Lett. 52(11), 900–902 (2016). [CrossRef]
6. K. Myny, “The development of flexible integrated circuits based on thin-film transistors,” Nat. Electron. 1(1), 30–39 (2018). [CrossRef]
7. K. Nomura, A. Takagi, T. Kamiya, H. Ohta, M. Hirano, and H. Hosono, “Amorphous oxide semiconductors for high-performance flexible thin film transistors,” Jpn. J. Appl. Phys. 45(5B), 4303–4308 (2006). [CrossRef]
8. C. Liu, Y. Xu, Y. Li, W. Scheideler, and T. Minari, “Critical Impact of Gate Dielectric Interfaces on the Contact Resistance of High-Performance Organic Field-Effect Transistors,” J. Phys. Chem. C 117(23), 12337–12345 (2013). [CrossRef]
9. C. Wang, Z. Hu, X. He, C. Liao, and S. Zhang, “One Gate Diode-Connected Dual-Gate a-IGZO TFT Driven Pixel Circuit for Active Matrix Organic Light-Emitting Diode Displays,” IEEE Trans. Electron Dev. 63(9), 3800–3803 (2016). [CrossRef]
10. W. Shin, H. Ahn, J. Na, S. Hong, O. Kwon, J. Lee, J. Um, J. Jang, S. Kim, and J. Lee, “A Driving Method of Pixel Circuit Using a-IGZOTFT for Suppression of Threshold Voltage Shift in AMLED Displays,” IEEE Electron Device Lett. 38(6), 760–762 (2017). [CrossRef]
11. J. Park, W. Maeng, H. Kim, and J. Park, “Review of recent developments in amorphous oxide semiconductor thin-film transistor devices,” Thin Solid Films 520(6), 1679–1693 (2012). [CrossRef]
12. K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature 432(7016), 488–492 (2004). [CrossRef] [PubMed]
13. J.-K. Jeong, J.-H. Jeong, H.-W. Yang, J.-S. Park, Y.-G. Mo, and H.-D. Kim, “High Performance Thin Film Transistors with Cosputtered Amorphous Indium Gallium Zinc Oxide Channel,” Appl. Phys. Lett. 91(11), 113505 (2007). [CrossRef]
14. Y.-H. Kim, J.-S. Heo, T.-H. Kim, S. Park, M.-H. Yoon, J. Kim, M.-S. Oh, G.-R. Yi, Y.-Y. Noh, and S.-K. Park, “Flexible Metal-Oxide Devices Made by Room-Temperature Photochemical Activation of Sol-Gel Films,” Nature 489(7414), 128–132 (2012). [CrossRef] [PubMed]
15. J.-K. Um, S.-H. Lee, S.-H. Jin, M. Mativenga, S.-Y. Oh, C.-H. Lee, and J. Jang, “High-Performance Homojunction a-IGZO TFTs with Selectively Defined Low-Resistive a-IGZO Source/Drain Electrodes,” IEEE Electron Device Lett. 62, 2212–2218 (2017).
16. N. Tiwari, R. Chauhan, H. Shieh, P. Liu, and Y. Huang, “Photoluminescence and Reliability Study of ZnO Cosputtered IGZO Thin-Film Transistors Under Various Ambient Conditions,” IEEE Trans. Electron Dev. 63(4), 1578–1581 (2016). [CrossRef]
17. Y. Chen, D. Geng, M. Mativenga, H. Nam, and J. Jang, “High-Speed Pseudo-CMOS Circuits Using Bulk Accumulation a-IGZO TFTs,” IEEE Electron Device Lett. 36(2), 153–155 (2015). [CrossRef]
18. X. Xu, Q. Cui, Y. Jin, and X. Guo, “Low-voltage zinc oxide thin-film transistors with solution-processed channel and dielectric layers below 150°C,” Appl. Phys. Lett. 101(22), 222114 (2012). [CrossRef]
19. J. Lee, I. Cho, J. Lee, and H. Kwon, “Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors,” Appl. Phys. Lett. 93(9), 093504 (2008). [CrossRef]
20. Y.-C. Han, M.-S. Lim, J.-H. Park, and K.-C. Choi, “ITO-free flexible organic light-emitting diode using ZnS/Ag/MoO3 anode incorporating a quasi-perfect Ag thin film,” Org. Electron. 14(12), 3437–3443 (2013). [CrossRef]
21. K. Nomura, T. Kamiya, H. Ohta, M. Hirano, and H. Hosono, “Defect passivation and homogenization of amorphous oxide thin-film transistor by wet O2 annealing,” Appl. Phys. Lett. 93(19), 192107 (2008). [CrossRef]
22. A. Wang, T. Chen, S. Lu, Z. Wu, Y. Li, H. Chen, and Y. Wang, “Effects of doping and annealing on properties of ZnO films grown by atomic layer deposition,” Nanoscale Res. Lett. 10(1), 75 (2015). [CrossRef] [PubMed]
23. S. J. Kim, S. Y. Lee, Y. W. Lee, W. G. Lee, K. S. Yoon, J. Y. Kwon, and M. K. Han, “Effect of channel layer thickness on characteristics and stability of amorphous hafnium-indium-zinc oxide thin film transistors,” Jpn. J. Appl. Phys. 50(2R), 024104 (2011). [CrossRef]
24. M. Mativenga, S. Hong, and J. Jang, “High current stress effects in amorphous-InGaZnO4 thin-film transistors,” Appl. Phys. Lett. 102(2), 023503 (2013). [CrossRef]
25. S. Lee, D. Jeong, M. Mativenga, and J. Jang, “Highly Robust Bendable Oxide Thin-Film Transistors on Polyimide Substrates via Mesh and Strip Patterning of Device Layers,” Adv. Funct. Mater. 27(29), 1700437 (2017). [CrossRef]
26. D. E. Walker, M. Major, M. B. Yazdi, A. Klyszcz, M. Haeming, K. Bonrad, C. Melzer, W. Donner, and H. von Seggern, “High mobility Indium Zinc Oxide Thin Film Field-Effect Transistors by Semiconductor Layer Engineering,” ACS Appl. Mater. Interfaces 4(12), 6835–6841 (2012). [CrossRef] [PubMed]
27. J.-C. Jeong, I.-H. Song, S.-I. Kim, S.-W. Kim, C.-J. Kim, J.-C. Lee, H.-G. Lee, E.-H. Lee, H. Yim, K.-L. Kim, K.-W. Kwon, and Y.-S. Park, “Self-aligned top-gate amorphous gallium indium zinc oxide thin film transistors,” Appl. Phys. Lett. 93, 053501 (2008). [CrossRef]
28. S. Lee, J. Shin, and J. Jang, “Top Interface Engineering of Flexible Oxide Thin-Film Transistors by Splitting Active Layer,” Adv. Funct. Mater. 27(11), 1604921 (2017). [CrossRef]