In this work, we report a CMOS comparable fabrication process of core-shell SiNW solar cell from single-crystalline p-type Si(100) test wafers. Optical lithography defined plasma etching was used to form highly ordered vertical SiNW arrays, which display a drastic reduction in optical reflectance over a wide range of wavelengths. BF2 and P ion implantations were employed for producing a sharp and shallow radial p-n junction. Under AM 1.5G illumination, the device demonstrates a short circuit current density (Jsc) of 14.2 mA/cm2, an open circuit voltage (Voc) of 0.485 V and a fill factor (FF) of 42.9%, giving a power conversion efficiency (PCE) of 2.95%. The Jsc observed is 52% higher than that in the control device with planar Si p-n junction, indicating significant enhancement in carrier generation and collection efficiency from the core-shell structure. Impact of series resistance (Rs) is also studied, highlighting potential improvement of PCE to 4.40% in the absence of Rs. With top contact optimized, PCE could further increase to 6.29%.
©2011 Optical Society of America
The research for energy supplies has always been one of the most important quests for generations. In the past decades, diminishing supplies in natural fuel resources and environmental issues from combustion gases highlight the need for new energy sources [1–3]. Being clean, renewable and universally abundant, solar energy is a viable choice to meet the increasing energy demand. The harvest and conversion of solar energy through semiconductor PV devices has been under research since 1950s. Currently, a dominant majority of commercial PV cell production consists of single junction planar Si PV cells. However, with its relatively low optical absorption coefficient [3,4], there is limited absorption of solar energy in single-crystalline Si near the p-n junction. Meanwhile, reasonable performance of the solar cell requires low-defect starting wafer, incurring high cost of purification .
SiNW based solar cell has the potential to address both issues. The anti-reflection property of SiNWs has been previously demonstrated [4,5]. Also, radial p-n junction formed by a core-shell structure decouples charge separation from light absorption, allowing for more effective carrier transport and collection in lower quality starting material . In previous studies, SiNWs were fabricated using “bottom-up” catalyst assisted VLS growth [7–10] or “top-down” patterned etching from Si wafers [11–14], and oppositely doped “shell” layer was formed by thin-film deposition [8–12] or diffusion . Power conversion efficiencies (PCEs) obtained were generally less than 1.5% [8–13]. Recombination problem arising from rough surfaces  and poor junction quality  is believed to be the main cause for these relatively low efficiencies. Single nanowire solar cell with radial p-i-n junction could attain an efficiency of 3% , but has limited potential for large-scale, low-cost production. In this work, radial junction SiNW array based solar cells are fabricated in a simple and scalable CMOS comparable process from cheap starting Si wafer, yielding efficiencies close to 3%. Ion implantation is used for core-shell formation for precise tailoring of junction depth.
2. Experimental details
Key steps in the experimental procedure are illustrated in Fig. 1 . The staring material is p-type Si(100) test wafer with resistivity in the range of 1-50 Ω cm. Back surface field (BSF)  is created by BF2 implant to form a highly doped p+ layer, in order to minimize carrier recombination at rear surface of the cell. The front surface was patterned using standard KrF deep ultraviolet (DUV) lithography followed by resist trimming in O2 plasma, to form a matrix of organic resist nano-hemispheres with diameter of 200 nm. The surface was etched in SF6 based plasma to form arrays of 1.6 um long SiNWs. Resist was then stripped in O2 plasma, and the wafer further cleaned in a sulfuric acid-hydrogen peroxide mixture (SPM) to remove any organic residual.
Two separate ion implantation processes were used for core and shell formation respectively [Fig. 1(h)]. The as-etched SiNW arrays first underwent a four-rotational BF2 implant with a dose of 2.5 x 1013 cm−2, energy of 80 keV and a vertical tilt angle of 7° for each rotation. The drive-in process was a furnace annealing at 1000 °C for 1 hour, to yield a more uniform distribution of p-type dopant in the wires. Subsequently, a similar four-rotational phosphorous implant was carried out with a dose of 1015 cm−2 and energy of 7 keV, followed by a 5 second rapid thermal annealing process at 1000 °C to convert the outer shell of the wires to n-type. The implant and annealing conditions were carefully tailored by simulation (T-SUPREM4) to ensure the formation of a uniform and shallow radial junction.
A continuous film of Ti/Cu with thickness of 100 nm/500 nm was sputtered onto the back surface of the cell as bottom electrode. Ti serves to provide better adhesion between Cu and Si surface, while Cu ensures high electrical conductance in the metal electrode. A similar Ti/Cu layer was then sputtered through a shadow mask to form metal grids on the front surface, thus completing the fabrication process of the SiNW based solar cell. Meanwhile, planar control device was created with similar starting wafer and under identical process conditions as fore-mentioned, omitting the plasma etching step for SiNW formation.
To facilitate I-V measurement, back surface of the device was fixed to a conductive substrate by silver paste, and a conductive rod was attached to front side metal grid as extended top electrode [Fig. 2(e) ]. Optical reflectance data was obtained using integrating sphere on a Shimazu UV 3600 UV-VIS-NIR Spectrometer. Electrical performance was tested and characterized under a standard AM 1.5G solar simulator.
3. Results and discussion
Figure 2 shows the SiNW device at various stages of fabrication. After DUV lithography patterning, a matrix of nano-hemispheres is formed on the top surface of Si wafer [Fig. 2(a)]. Such excellent uniformity and periodicity persists in the SiNWs etched, which are approximately 1.6 um long and 200 nm in diameter [Fig. 2(b)]. They are observed to have a smooth outer surface, without any visible rough patch or surface defect. The vertical SiNWs with inter-wire spacing of 200 nm take up approximately 30% of the entire array volume. Near the front surface where top electrode is deposited, voids are seen between nanowires beneath the metal layer [Fig. 2(c)], which could be attributed to the limited gap-filling ability of the sputtering process. Nonetheless, Ti adheres to SiNW surface in a rather conformal manner [Fig. 2(d)], assuring an effective barrier between Cu and Si to avoid possible degradation of carrier lifetime caused by Cu diffusion. The metal grid covers approximately 30% of the entire 1 x 1 cm2 top surface [Fig. 2(e)].
3.1 Optical reflectance measurement
SiNW device displays a darker surface under visible light as compared to planar control device [Fig. 2(d)], indicating less optical reflection on the top surface of the device. This observation is confirmed by reflectance measurement using integrating sphere. The percentage reflectance values at various wavelengths are plotted in Fig. 3(a) . A comparison between the data for planar Si and SiNW surface shows a drastic decrease in reflectance between 300 nm to 1200 nm. The slight discontinuity of the curves observed at around 830 nm is caused by switching of photodetector by the spectrometer at this particular wavelength. Reflectance of planar Si is generally above 30% over the entire range of wavelengths measured, while reflectance of SiNW surface is suppressed to less than 12%.
For a quantitative analysis of the change in total incident power reflected, incident spectral irradiance under AM 1.5G illumination [Fig. 3(b) inset] are multiplied by corresponding percentage reflectance values, to obtained the reflected spectral irradiance from 300nm to 1200 nm [Fig. 3(b)]. Total percentage of incident irradiance reflected over the entire range of wavelengths is calculated. It is found that planar Si surface reflects 32% of the total incident irradiance, while SiNW surface reflects only 2.7%, a 92% suppression as compared to planar surface. The sub-wavelength diameter of the wires is responsible for more effective light scattering and light trapping [13,14,16]. Thus even with a moderate filling ratio of 30% and a length of only 1.6 um, the SiNW array is able to reduce total reflection of incident solar irradiance to only 8% of that reflected by planar Si surface.
3.2 Simulation of surface dopant profile
As high resistance in depletion region is undesirable for collection of light generated carriers , it has been remarked that depletion width in the nanowires must be kept small . This requires the formation of a highly doped p-n junction. Because of insufficient doping in the starting wafer (~1016 cm−3), a core doping step is essential to increase boron concentration, so as to reduce the depletion width and to ensure a un-depleted core needed for transport of holes. A four-rotational ion implant is used for both core and shell doping, with conditions (implant dose, energy and tilt angle) pre-determined by numerical simulation using T-SUPREM4. The result of simulation demonstrates that after the core implant and drive-in, boron concentration has been increased to approximately 7 x 1017 cm−3 in the core of the nanowires [Fig. 4(a) ]. The subsequent shell implant forms a thin and uniform n+ sheath, with a phosphorous concentration of around 1021 cm−3 on the wire surface [Fig. 4(b)]. The p-n interface is located at around 50 nm under the nanowire outer surface, where both boron and phosphorous concentrations are approximately equal. Assuming non-degeneracy in Si, build-in voltage of the p-n junction is estimated to be 1.06 V according to Eq. (1) :Eq. (2) :Fig. 4(c)]. If boron concentration were to remain at its initial value (~1016 cm−3), depletion width would increase to around 350 nm based on Eq. (1) and (2), leaving the entire wire depleted, thus highlighting the necessity of BF2 core implant.
3.3 I-V characterization
The electrical characteristics of core-shell SiNW based and Si planar solar cell are tested under a solar simulator, and summarized in Table 1 . As the devices have top area of 1 x 1 cm2, the currents measured are equivalent to the values of current density. From the I-V curve of SiNW device under dark and AM 1.5G illumination [Fig. 5(a) ], a clear rectifying behavior is observed. An expanded I-V plot in forward bias [Fig. 5(b)] shows that SiNW device has an open circuit voltage (Voc) of 0.485 V, a short circuit current density (Jsc) of 14.2 mA/cm2 and a fill factor (FF) of 42.9%. The PCE is calculated to be 2.95%, which is significantly higher than that of previously reported SiNW based solar cells with radial p-n junction [8–13]. Jsc and Voc of the planar Si control device is found to be 0.548 V and 9.34 mA/cm2 respectively. The 52% increase of Jsc in SiNW based device is attributed to improved light absorption in SiNW arrays and increased junction area from the radial p-n junction. However, it should be remarked that identical four-rotational ion implantation processes are used for junction formation in both SiNW and planar Si device. For SiNW device, each of the four implants is responsible for doping a vertical nanowire from a different angle, thus the dopant ions are not all incident onto the same plane. While for planar Si device, the top surface receives all incident dopant ions in four implants, thus forming a p-n junction with possibly higher dopant concentration and more severe substrate damage. As a result, the low Jsc in planar device could be partially attributed to recombination caused by ion implantation-induced defects.
A closer analysis of the dark I-V characteristic in reverse bias region [Fig. 5(c)] gives a leakage current of 65 uA at −1 V for SiNW based devices, as opposed to that of 21 uA for planar Si device. Sign of early reverse breakdown is observed for both devices, as a result of a large number of recombination centers caused by high doping at p-n junction [13,17]. Larger leakage current in SiNW based device indicates more recombination as compared to planar Si device, despite the latter having possibly more ion implantation-induced defects near the junction in planar Si device. This observation could be explained by the drastic increase of surface/junction area in SiNW arrays, which creates significantly more recombination sites and results in a higher overall recombination current in SiNW device. By plotting forward bias dark I-V data in a semi-log scale [Fig. 5(d)], local ideality factor n could be extracted from the slope. A plot of n in forward bias region is shown in Fig. 5(e). For SiNW based device, n is 2-2.5 between 0.3 to 0.55 V. There are possibly recombination losses via defects in bulk Si, on nanowire surfaces, at the radial p-n junctions and in the depletion region. Planar Si control device has an ideality factor of 1.5 at around at 0.55 V, confirming less overall recombination. The large peak of n for planar Si device is under the effect of shunt resistance arising from the fabrication process, rather than the design and structure of the cell. The major increase in n of SiNW device after 0.6 V could be under the impact of series resistance .
In order to quantify the effect of series resistance Rs on device performance, multiple illumination intensity method  is employed to evaluate Rs for both SiNW and Si planar solar cells, as demonstrated in Fig. 6 . I-V data are obtained under four different illumination intensities. For every I-V curve, a constant arbitrary small change in light-generated current ∆IL is defined, to located the data point in the fourth quadrant such that |I| = Isc − ∆IL [Fig. 6(a)]. These four points obtained are fitted with a linear regression line, which has a slope of 1/Rs . Rs of SiNW based device is extracted to be 12.9 Ω [Fig. 6(a)], nearly 14 times larger than that of planar Si control device [Fig. 6(b)]. This result is consistent with the difference in surface topology between the two devices. The deposited metal layer is thinner on the sidewalls of high-aspect-ratio nanowires than that on planar surfaces [Fig. 2(c)], resulting in higher resistance in the top metal electrode for SiNW device. Meanwhile, for regions without direct contact to top metal grid, carriers generated in the radial junctions need to travel down the nanowires before being transported to respective electrodes. The long and narrow geometry of the wires therefore contributes to larger resistance.
The relatively high overall efficiency obtained in this core-shell SiNW based solar cell is mainly contributed by light generated current, which indicates an efficient carrier generation-collection process achievable through this design, even with relatively large resistivity in the starting wafer. To compensate for the short carrier diffusion length associated with defects in the starting wafer, a short collection path is created by using nanowires with small radius (~100 nm). Meanwhile, the four-rotational ion implantation process enables formation of a shallow and highly-doped radial p-n junction, keeping the depletion region small. High carrier mobility near the junction coupled with short collection length effectively reduces loss in Jsc caused by recombination.
To further improve the device performance, series resistance needs to be reduced as it is the main cause for low FF. I-V curve of the solar cell under the impact of Rs is given by :Fig. 7 . Upon eliminating the effect of Rs, FF of SiNW device could improve from 42.9% to 63.9%. This potential improvement observed is significantly lesser in planar control device, as a result of its having a much smaller Rs. Also, an empirical expression of FF in the absence of parasitic resistances was proposed by M. A. Green , that calculates FF directly from Voc and ideality factor n of the device. These two methods yield similar estimated values of “intrinsic” FF.
FF and PCE without the effect of Rs are also presented in Table 1. It is shown that although PCE of SiNW device fabricated suffered from low FF, it could increase to 4.40% upon eliminating Rs, surpassing the efficiency of planar device. Lower series resistance and higher FF could be achieved by improving experimental techniques. Recent research has demonstrated that a complete filling of metal between nanowires on the top surface helps to achieve FF as high as 60.7% . Deposition techniques such as electroplating would be useful to improve the gap filling of metal in this work.
Meanwhile, there is limitation in junction formation by ion implantation. An inter-wire spacing of 200 nm is sufficient for incident ions with 7° tilt to reach the bottom of 1.6 um nanowires, if the wire diameter remains constant throughout the entire length. However, because of the tapered structure of our SiNWs [Fig. 2(b)], surface dopant concentration in the part of the nanowires below 1.25 um might be less than that in the simulated dopant profile (Fig. 4), under the shadowing effect from neighboring nanowires during ion implantation. This issue could be solved by adopting a more conformal doping method such as plasma doping.
In addition, 30% of the top surface is currently covered a 600 nm thick metal layer, which effectively prevents incident light from reaching the wires below. If the design of metal grid is optimized to minimize these shading losses, a larger Jsc of 20.3 mA/cm2 and a PCE of 4.21% could be attained for SiNW device. Combining with the elimination of series resistance, PCE could further increase to 6.29% (Table 1). Furthermore, as optical reflectance continues to decrease with nanowires lengths above 2 um , it is possible to further improve light absorption and overall device performance if longer wires are fabricated.
In conclusion, we demonstrate the design and fabrication of core-shell SiNW solar cell based on Si wafers which are not optimized for solar application. The SiNWs produced using DUV lithography patterned plasma etch display drastic reduction in optical reflectance over a wide range of wavelengths, leading to a 92% suppression in total reflection of incident irradiance as compared to Si planar surface. Jsc obtained (14.2 mA/cm2) is 52% higher than that of Si planar control device, and contributes to an overall PCE of 2.95%. Low FF (42.9%) is mainly caused by large series resistance (12.9 Ω), which needs to be reduced by improving the quality of metal contact on SiNWs. With effect of series resistance and metal grid shading losses eliminated, PCE is estimated to be 6.29% with a Jsc of 20.3 mA/cm2.
This work is supported by Institute of Microelectronics under Agency for Science, Technology and Research (A*STAR) Singapore and Silicon Nano Device Laboratory at Department of Electrical and Computer Engineering, National University of Singapore. Helpful discussions and support from fellow research students in Professor Lee Sungjoo’s group is gratefully acknowledged.
References and links
3. G. Goncher, and R. Solanki, “Semiconductor nanowire photovoltaics,” Proc. SPIE 7047, 70470L–1 – 70470L–14 (2008).
4. L. Tsakalakos, J. Balch, J. Fronheiser, M. Y. Shih, S. F. LeBoeuf, M. Pietrzykowski, P. J. Codella, B. A. Korevaar, O. Sulima, J. Rand, A. Davuluru, and U. Rapol, “Strong broadband optical absorption in silicon nanowire films,” J. Nanophotonics 1, 013552 (2007). [CrossRef]
5. M. D. Kelzenberg, S. W. Boettcher, J. A. Petykiewicz, D. B. Turner-Evans, M. C. Putnam, E. L. Warren, J. M. Spurgeon, R. M. Briggs, N. S. Lewis, and H. A. Atwater, “Enhanced absorption and carrier collection in Si wire arrays for photovoltaic applications,” Nat. Mater. 9(3), 239–244 (2010). [CrossRef] [PubMed]
6. B. M. Kayes, H. A. Atwater, and N. S. Lewis, “Comparison of the device physics principles of planar and radial p-n Junction nanorod solarc,” J. Appl. Phys. 97, 114302 (2005). [CrossRef]
7. B. Tian, X. Zheng, T. J. Kempa, Y. Fang, N. Yu, G. Yu, J. Huang, and C. M. Lieber, “Coaxial silicon nanowires as solar cells and nanoelectronic power sources,” Nature 449(7164), 885–889 (2007). [CrossRef] [PubMed]
8. L. Tsakalakos, J. Balch, J. Fronheiser, B. A. Korevaar, O. Sulima, and J. Rand, “Silicon nanowire solar cells,” Appl. Phys. Lett. 91, 233117 (2007). [CrossRef]
9. M. D. Kelzenberg, D. B. Turner-Evans, B. M. Kayes, M. A. Filler, M. C. Putnam, N. S. Lewis, and H. A. Atwater, “Photovoltaic measurements in single-nanowire silicon solar cells,” Nano Lett. 8(2), 710–714 (2008). [CrossRef] [PubMed]
11. K. Peng, X. Wang, and S. T. Lee, “Silicon nanowire array photoelectrochemical solar cells,” Appl. Phys. Lett. 92, 163103 (2008). [CrossRef]
13. X. Wang, K. L. Pey, C. H. Yip, E. A. Fitzgerald, and D. A. Antoniadis, “Vertically arrayed Si nanowire/nanorod-based core-shell p-n junction solar cell,” J. Appl. Phys. 108, 124303 (2010). [CrossRef]
15. M. A. Green, A. W. Blakers, J. Shi, E. M. Keller, and S. R. Wenham, “High-efficiency silicon solar cells,” IEEE Trans. Electron. Dev. 31(5), 679–683 (1984). [CrossRef]
17. S. M. Sze, and K. K. Ng, Physics of Semiconductor Devices (Wiley, New York, 2007).
18. M. Wolf and H. Rauschenbach, “Series resistance effects on solar cell measurements,” Adv. Energy Convers. 3(2), 455–479 (1963). [CrossRef]
19. M. A. Green, “Solar cell fill factors: general graph and empirical expressions,” Solid-State Electron. 24(8), 788–789 (1981). [CrossRef]
20. C. Honsberg, and S. Bowden, “PVCDROM: Measuring ideality factor,” (Photovoltaic Education Network, 2010). http://www.pveducation.org/pvcdrom/characterisation/measurement-of-ideality-factor.
21. D. K. Schroder, Semiconductor Material and Device Characterization (Wiley, New Jersey, 2005).