## Abstract

In this paper, a Mach-Zehnder silicon nanoplasmonic electro-optic modulator is proposed and theoretically analyzed. It is composed of horizontal metal-SiO_{2}-Si-metal plasmonic slot waveguides for phase shifting and ultracompact V-shape splitter/combiner to link the plasmonic slot waveguides and the conventional Si dielectric waveguides. The proposed modulator can be directly integrated into existing Si electronic photonic integrated circuits (EPICs) and be fabricated using standard Si complementary metal-oxide-semiconductor (CMOS) technology. The modulator’s parameters are optimized through systematic 2-dimensional numerical simulations. For a modulator with 3-µm-long Ag-SiO_{2}(2 nm)-Si(50 nm)-Ag phase shifter and 0.35-µm-long splitter/combiner operating at 1.55-µm wavelength, simulation shows an insertion loss of ~–8 dB, an extinction ratio of ~7.3 dB — with a switching voltage of ~5.6 V, and a bandwidth of ~500 GHz. A possible approach to reduce the switching voltage is addressed.

©2010 Optical Society of America

## 1. Introduction

Owing to the capability of nanoscale light confinement, plasmonic devices, which are based on surface plasmon polariton (SPP) excitation and propagation at metal-dielectric interfaces, show potential for applications in Si electronic photonic integrated circuits (EPICs) to bridge the length-scale mismatch between the diffraction-limited dielectric photonic devices and the nanoscale electronic devices [1–4]. Various passive (e.g., waveguides [5,6], interferometers [7], resonators [8], coupler [9,10], splitter [11], and antennas [12], etc.) and/or active plasmonic devices (e.g., emitters [13], photodetectors [14], and plasmonic modulators [15,16], etc.) have been demonstrated recently. Among them, an ultracompact Si complementary metal-oxide-semiconductor (CMOS) compatible electrooptic (EO) plasmonic modulator would be highly desired because state-of-the-art Si modulators suffer a drawback of large footprint (with millimeter length) and poor scaling characteristics due to the weak nonlinear optical effects in Si (e.g., free carrier dispersion effect) [17]. However, although many kinds of plasmonic modulators have been proposed or demonstrated [18], most of them require unique active materials which are not fully compatible to the standard Si CMOS technology, such as CdSe quantum dots [19], ferroelectric materials [20], and liquid crystals [21], or are based on effects other than EO, such as thermooptic effect [22], magnetooptic effect [23], acoustooptic effect [24], and all-optical modulation [25]. In terms of integrating modulators into conventional Si-waveguide based EPICs, it is desirable to use Si as the active material. Such a Si EO plasmonic modulator was demonstrated by Dionne et al recently, based on multimode interfereometry between a photonic mode and a plasmonic mode simultaneously supported by the vertical metal-SiO_{2}-Si-metal plamonic waveguide [15]. However, Dionne’s modulator contains a centimeter-scale suspended Si membrane with metal deposited on both sides, requiring a micro-electro-mechanical-systems (MEMS) type manufacturing process, making it difficult to be integrated in existing Si EPICs using standard Si CMOS technology.Here, we propose a new design for a Si EO plasmonic modulator as shown schematically in Fig. 1
. The modulator has a Mach-Zehnder interferometer (MZI) configuration and is directly implemented using a conventional Si dielectric waveguide scheme. It is composed of horizontal metal-SiO_{2}-Si-metal plasmonic slot waveguides for phase shifting and simple V- shape splitter/combiner to link the plasmonic waveguides and the Si dielectric waveguide. The

device can be fabricated using the standard Si CMOS technology, recently developed for gate-all-around MOSFETs and/or FinFETs [26]. Moreover, unlike Dionne’s modulator, the plasmonic waveguide in our modulator supports only the plasmonic mode. The effective plasmonic modal index is modulated by an applied voltage through the Si free carrier dispersion effect. Compared to Dionne’s modulator, our modulator offers advantages of even smaller footprint, easier on-chip integration, and simpler fabrication.

The remainder of the paper is organized as follows. Section 2 describes the 2-dimensional (2-D) optical simulation method using the commercial software FullWAVE from RSOFT [27]. Then, the optical properties of various plasmonic slot waveguides and 1 × 2 splitters are systematically investigated in Sections 3 and 4, respectively, to optimize the modulator’s parameters. Section 5 presents the optical properties of our modulators. Section 6 analyzes the electrical properties of the MOS-type plasmonic slot waveguide for phase shifting. Finally, the key findings are summarized in Section 7.

## 2. Optical simulation method

The FullWAVE from RSOFT, which is based on a finite-difference time-domain (FDTD) method [27], is used in this work. A very fine and un-uniform grid (e.g., 1 nm at the bulk and 0.2 nm near the interface) is set to accurately capture the field change around the very thin gate oxide thickness of our MOS-type plasmonic slot waveguides. Because the 3-D FDTD simulation with such a fine grid size needs a very long computational time, the 2-D FDTD simulation is used in this work for simplification, which corresponds to an infinitely thick device shown in Fig. 1. The validity of such a simplification is discussed in the next section. A fundamental transverse electric (TE) mode light (the electric field is parallel to the x-axis) is launched in the conventional single-mode Si waveguide and then squeezed into the plasmonic slot waveguide through a simple taper coupler similar to that reported by Chen et al. [10]. A perfectly matched layer (so called PML) is used to attenuate the field within its region without back reflection. Silver is used as the metal because it has low loss in the wavelength around 1.55 µm and has been widely used in the plasmonic devices. Copper and aluminum, – they are the Si-CMOS compatible materials, are also considered. The build-in optical parameters for these metals in RSOFT are used. The refractive indices of Si and SiO_{2} are set to be 3.455 and 1.445, respectively. Figure 2(a)
shows a typical structure which has a 400-nm-wide Si waveguide and a Ag-SiO_{2}(5 nm)-Si(50 nm)-Ag MOS-type plasmonic slot waveguide. Figure 2(b) shows the field distribution in this structure launched by 1.55-µm light. The coupling efficiency is calculated by normalizing the power detected by a power monitor placed in the plasmonic waveguide near the coupler (e.g., point A in Fig. 2(b)) with respect to the input power. The propagating electric field, E(x,z), in the plasmonic slot waveguide along the z direction can be generally expressed as:

_{eff}is the real effective modal index, L

_{p}is the propagation length, and λ

_{0}is the free-space wavelength. The SPP waves at different points in the plasmonic waveguide (e.g., points A and B in Fig. 2(b)) are monitored as a function of time, as shown in Fig. 2(c) for example. Then, n

_{eff}is calculated from the phase variation and L

_{p}is calculated from the amplitude decay of these two waves. It was noticed that the mode-solver approach based on beam propagation method (BPM) from RSOFT does not give reasonable n

_{eff}and L

_{p}values for our nanoscale plasmonic slot waveguides.

To verify the accuracy of this approach, a conventional Si waveguide is simulated to extract n_{eff} and L_{p} values. The n_{eff} and L_{p} values are also calculated from the full vectorial mode-solving approach. The difference in n_{eff} and L_{p} values calculated from the different approaches is less than 2%. We also simulate a direct coupler from a 300-nm Si waveguide to Ag-air(40 nm)-Ag plasmonic slot waveguide. The coupling efficiency is ~67%, close to that reported by Veronis et al who simulated the same structure with a different method [28].

## 3. MOS-type plasmonic slot waveguides

Figure 3
shows the normalized electric field distributions in Ag-SiO_{2}(50 nm)-Ag, Ag-Si(50 nm)-Ag, and Ag-SiO_{2}(5 nm)-Si(45 nm)-Ag waveguides as well as their n_{eff} and L_{p} values. The optical property of a metal-dielectric-metal (MDM) plasmonic slot waveguide depends strongly on the dielectric-core’s index. It is seen that n_{eff} increases and L_{p} reduces accordingly when the dielectric-core’s index increases. For the Ag-SiO_{2}-Si-Ag plasmonic slot waveguide, the electric-field in the low-index SiO_{2} region is dramatically enlarged due to the displacement field continuity across the Si-SiO_{2} interfaces. Namely, the SPP modal power appears to concentrate into the low-index region. The same observation is also reported by other groups [29,30]. The Ag-SiO_{2}(5 nm)-Si(45 nm)-Ag waveguide has the n_{eff} and L_{p} values between those of Ag-SiO_{2}(50 nm)-Ag and Ag-Si(50 nm)-Ag waveguides. Moreover, only the bound SPP mode is supported in the MDM plasmonic slot waveguide with the slot (the dielectric core) width of less than ~100 nm [5].

In the Si EO modulators, the real refractive index of Si (n_{Si}) is modulated by an applied voltage through the Si EO effect. Thus, it is important to know the dependence of the optical properties (i.e., n_{eff} and L_{p}) on n_{Si} for a plasmonic slot waveguide to be used as a phase shifter. Figure 4
shows n_{eff} and L_{p} as a function of n_{Si} for Ag-Si(W_{SiO2})-Si(50 nm)-Ag plasmonic slot waveguides with the SiO_{2} width (W_{SiO2}) of 0, 2, 5, and 10 nm, respectively. We can see that both n_{eff} and L_{p} depend on n_{Si} almost linearly, at least around its initial value of 3.455. Therefore, *d*L_{p}/*d*n_{Si} and *d*n_{eff}/*d*n_{Si} can be defined for a certain plasmonic slot waveguide. These values, extracted from linearly fitting the data points obtained from the FDTD simulation, are also indicated in Fig. 4. The *d*n_{eff}/*d*n_{Si} value, which reflects the phase modulation efficiency through n_{Si}, is one of the key properties for our MOS-type plasmonic slot waveguide to be used as a phase shifter and is as larger as better. A large value of *d*L_{p}/*d*n_{Si} is also better because the increased L_{p} due to the reduced n_{Si} can partially compensate the free carrier absorption induced L_{p} reduction. We can see from Fig. 4 that the thin SiO_{2} layer in the MOS-type plasmonic slot waveguides plays a key role, not only in n_{eff} and L_{p}, but also in *d*n_{eff}/*d*n_{Si} and *d*L_{p}/*d*n_{Si}.

To further evaluate the influence of thin SiO_{2} layer in the Ag-SiO_{2}-Si-Ag plasmonic slot waveguides, the total slot width is fixed at 50 nm while the SiO_{2} width increases from 0 to 50 nm and the Si width (W_{Si}) decreases from 50 to 0 nm accordingly. Figures 5(a), (b) and (c)
depict the n_{eff}, L_{p}, and *d*n_{eff}/*d*n_{Si} values as a function of W_{SiO2}, respectively, where the 0-nm SiO_{2} corresponds to the Ag-Si(50 nm)-Ag waveguide and the 50-nm SiO_{2} corresponds to the Ag-SiO_{2}(50 nm)-Ag waveguide. We can see that both n_{eff} and *d*n_{eff}/*d*n_{Si} decrease, and L_{p} increases monotonically, with increasing W_{SiO2}, more quickly at the thinner SiO_{2} region. For the Si EO modulator applications, one needs a large *d*n_{eff}/*d*n_{Si} for efficient phase modification and a large L_{p} for small insertion loss. For a certain Δn_{Si} (which can be achieved through the Si EO effect), one may define product of *d*n_{eff}/*d*n_{Si} and L_{p} as the figure of merit for the SiO_{2} width optimization. Figure 5(d) depicts the values of *d*n_{eff}/*d*n_{Si} × L_{p} as a function of W_{SiO2}. This product also decreases monotonically with increasing W_{SiO2}, indicating that a thinner SiO_{2} width in the MOS-type plasmonic slot waveguide is better for the phase shifter usage. In modern Si CMOS technology, the gate oxide thickness has been scaled down to less than 1.5 nm [31]. In this study, the gate oxide in the MOS-type plasmonic slot waveguide is varied between 2 and 10 nm to investigate its effect on the overall modulator performances.

For comparison, we investigate *d*n_{eff}/*d*n_{SiO2} as a function of W_{SiO2}. The result is depicted in Fig. 5(e). We can see that *d*n_{eff}/*d*n_{SiO2} increases quickly with W_{SiO2} increasing, reaches a maximum of ~1.68 at W_{SiO2} = ~25 nm, and then it decreases slowly with W_{SiO2} further increasing. This behavior can be attributed to concentration of the SPP modal power in the low-index SiO_{2} region, as shown in Fig. 3(c). It indicates that modification of n_{SiO2} is more effective than modification of n_{Si} in the MOS-type plasmonic slot waveguide for phase shifting. Unfortunately, SiO_{2} has no useful EO effect. On the other hand, dielectrics such as LiTaO_{3} have large EO effect (e.g., Pockels effect), plasmonic modulators using such an EO dielectric material have already been proposed in literature [32]. The detailed analysis of this kind of plasmonic modulator (i.e., EO dielectric material based) is out of the scope of this paper.

The influence of Si width on the Ag-SiO_{2}-Si-Ag plasmonic slot waveguides with the gate oxide thickness of 0, 1, 2, 5, and 10 nm are revealed in Fig. 6
, where n_{eff}, L_{p}, and *d*n_{eff}/*d*n_{Si} values are depicted as a function of W_{Si}, ranging from 10 to 100 nm. For the conventional Ag-Si-Ag waveguide, n_{eff} decreases and L_{p} increases monotonically with W_{Si} increasing, in good agreement with that calculated using the effective-index approach [33]. Meanwhile, n_{eff} decreases and L_{p} increases with W_{SiO2} increasing for waveguides with a certain W_{Si}, in agreement with that of Fig. 5.

The *d*n_{eff}/*d*n_{Si}
*vs.* W_{Si} curve when the SiO_{2} thickness is set to zero shows a very different behavior from the rest of the curves generated with non-zero SiO_{2} thickness. For the Ag-Si-Ag waveguides, the *d*n_{eff}/*d*n_{Si} value is always larger than 1 and it decreases monotonically to approach unity with W_{Si} increasing, which can be understood that n_{eff} of the Ag-Si-Ag waveguide is always larger than n_{Si} and it approaches to n_{Si} when W_{Si} is sufficiently large [33]. For the Ag-SiO_{2}-Si-Ag waveguides, on the other hand, the increase in W_{Si} has two contrary effects on *d*n_{eff}/*d*n_{Si}. Firstly, the increase of W_{Si} leads to the increase of the ratio of SPP power distributed in the Si region, which leads to the increase of *d*n_{eff}/*d*n_{Si}. Secondly, n_{eff} decreases with W_{Si} increasing, as shown in Fig. 6(a), which leads to the decrease of *d*n_{eff}/*d*n_{Si}. For the Ag-SiO_{2}(1 nm)-Si-Ag waveguides, the second effect dominates for the whole W_{Si} range (i.e., 10-100 nm), making the *d*n_{eff}/*d*n_{Si} value decreases monotonically with W_{Si} increasing. For the Ag-SiO_{2}(2 nm)-Si-Ag waveguides, the first effect dominates in the small W_{Si} region whereas the second effect prevails at the large W_{Si} region, thus the *d*n_{eff}/*d*n_{Si} value reaches a maximum of ~1.2 at W_{Si} = ~30–80 nm. For the plasmonic waveguides with SiO_{2} larger than ~5 nm, the first effect dominates over the whole W_{Si} range, with *d*n_{eff}/*d*n_{Si} value increasing monotonically with increasing W_{Si}, approaching unity when W_{Si} is larger than ~60 nm. Although L_{p} of all plasmonic waveguides increases monotonically with increasing W_{Si}, modification of the free carrier concentration in a Si MOS capacitor, − which causes the Si refractive index modification, can be made by an applied voltage only in a narrow region near the SiO_{2}/Si interface, as revealed in Section 6. Here, we just set W_{Si} = 50 nm for our modulators. The propagation loss of the Ag-SiO_{2}(2 nm)-Si(50 nm)-Ag waveguide is calculated to be ~1.9 dB/μm.

The 3-D FDTD simulations are also performed to evaluate the thickness effect of real devices. To do so, a relatively large grid size (i.e., 5 nm (bulk) /1 nm (interface) at x-axis, 25 nm (bulk) / 5 nm (interface) at y-axis and z-axis) is set to control the computational time to an acceptable level. Figure 7
shows the extracted n_{eff} and L_{p} values for Ag-Si(50 nm)-Ag, Ag-SiO_{2}(2 nm)-Si(50 nm)-Ag, Ag-SiO_{2}(5 nm)-Si(50 nm)-Ag, and Ag-SiO_{2}(10 nm)-Si(50 nm)-Ag waveguides as a function of the thickness ranging from 0.2 to 1 µm. For all waveguides, n_{eff} increases slightly with the thickness increasing from 0.2 to ~0.4 µm and then saturates to a value very close to that extracted from the 2-D simulation. L_{p} also exhibits similar behavior, but the saturation values are slightly smaller than those from the 2-D simulation, probably due to the power loss at the waveguide corners in the 3-D case. In literature, it was also reported that the thickness dependence of plasmonic slot waveguides becomes weak with the thickness increasing [34,35]. These results verify the feasibility of the 2-D simulation used in this study.

## 4. Nanoplasmonic splitter

A simple V-shape 1 × 2 splitter is designed, as shown schematically in the inset of Fig. 8(a)
, to deliver light from the Si dielectric waveguide to two plasmonic slot waveguides. The splitter has the same SiO_{2} layer as the plasmonic slot waveguide so that it can be fabricated simultaneously with the MOS-type plasmonic slot waveguide without additional processing steps. For a certain Si waveguide and plasmonic slot waveguides, the only parameter to be optimized is the splitter length. Figure 8(a) shows the coupling efficiencies from the 400-nm-wide Si waveguide to two identical plasmonic slot waveguides through a splitter with the length ranging from 0 (corresponding to the direct coupling) to 2.0 µm. The coupling efficiency for the direct coupling configuration (i.e., the splitter length is 0) is very small due to the strong light reflection at the interface between the dielectric Si waveguide and the plasmonic slot waveguides. The reflection coefficient decreases steeply while the coupling efficiency increases quickly with increasing splitter length, reaching a maximum of ~38% at each branch for the splitter with length of ~0.2–0.4 µm, corresponding to ~1.19 dB coupling loss. The coupling efficiency deceases slowly as the splitter length further increases due to increasing propagation losses along the splitter. The data points in Fig. 8(a) show damping with the length, especially in the range around the maximum coupling efficiency. The oscillation of the coupling efficiency with the splitter length can be attributed to the Fabry-Perot (FP) resonance inside the splitter [10]. At some points, the coupling efficiency as high as ~42% is obtained, corresponding to ~0.75 dB coupling loss. Figure 8(b) shows one example of the field distribution where 1.55-µm light is delivered from the 400-nm-wide Si waveguide into two Ag-SiO_{2}(2 nm)-Si(50 nm)-Ag plasmonic slot waveguides through a 0.35-µm long splitter. We can see that the light wave from the Si waveguide excites SPPs along the metal-dielectric boundaries in the splitter and the SPPs are “funneled” into two plasmonic slot waveguides identically. The coupling efficiency for each branch is 41.9%. Moreover, we can see that the coupling property of our splitter depends weakly on the oxide thickness of the MOS-type plasmonic slot waveguides. Therefore, the same length splittercan be used for plasmonic slot waveguides with different oxide thicknesses.

In the above design, the splitter is symmetric along the centerline of Si waveguide in order to deliver the same amount of light into each branch. The splitting ratio between two branches can be easily controlled by shifting the starting point of the V-shape splitter from the waveguide centerline, as shown schematically in the inset of Fig. 9(a)
. For the 0.35-μm-long splitter, the normalized powers at the left and right branches are shown in Fig. 9(a) as a function of the displacement of the starting point of the V-shape splitter from the Si waveguide centerline. The coupling efficiency into the left branch decreases significantly and the coupling efficiency into the right branch increases accordingly with the displacement increasing from 0 to ~60 nm. With the displacement further increasing, the coupling efficiency into the right branch also decreases quickly due to the strong light reflection at the metal/dielectric interface. For example, Fig. 9(b) shows the field distribution for light delivering from 400-nm-wide Si waveguide to two Ag-SiO_{2}(2 nm)-Si(50 nm)-Ag plasmonic waveguides through an asymmetric splitter with 0.35-µm length and 60-nm displacement. The coupling efficiencies to the left and right branches are 17.7% and 56.8%, respectively.

It is well known that the optical bandwidth of the MZI modulator is mainly limited by the splitter and combiner [17]. To evaluate the optical bandwidth of our splitter, the coupling efficiency for light delivering from the 400-nm-wide Si waveguide to two plasmonic slot waveguides through a symmetric 0.35-µm-long splitter is calculated for wavelength ranging from 1.05 to 2.05 µm. The results are depicted in Fig. 10
for various plasmonic slot waveguides. The damping of the data points can also be attributed to the FP resonance inside the splitter. Except the damping, we can see that the coupling efficiency for all plasmonic slot waveguides depends on wavelength weakly in the range of λ_{0} ≥ ~1.5 μm, indicating that our splitter can operate at a broad frequency range. In the range of λ_{0} < ~1.5 µm, the coupling efficiency decreases substantially with decreasing wavelength, most probably due to the increase of metal absorption loss in the splitter because the permittivity of silver depends strongly on wavelength at the range of λ_{0} < ~1.5 µm [36].

The combiner is a functional inverter of the splitter. It could be assumed that the combiner has the same optical property as the splitter. Here, a symmetric Λ-shape combiner is designed accordingly, which has exactly the same geometry as the V-shape splitter. Therefore, the input and output facets of our modulator are reversible.

## 5. Si MZI nanoplasmonic modulator

Based on the above analysis, a Si MZI nanoplasmonic modulator is designed, as shown in Fig. 1 and is in turn inserted into a conventional 400-nm-wide Si dielectric waveguide. The phase shifter is the 3-µm-long Ag-SiO_{2}-Si(50 nm)-Ag MOS-type plasmonic slot waveguides and the splitter/ combiner is 0.35-µm long. The Si index in one of the MOS-type plasmonic slot waveguides changes from 3.055 to 3.555, whereas the Si index in the other parts of modulator keeps 3.455. A 1.55-µm TE mode light is launched at the input Si waveguide and the light power at the output Si waveguide is monitored. Beside Ag, Cu and Al are also used as the metal.

Figure 11
shows the normalized output power in the dB scale as a function of n_{si} variation (Δn_{Si}) in one arm. As expected, the output light power is modulated by Δn_{Si}. For the Ag-SiO_{2}-Si(50 nm)-Ag modulators, the total insertion losses at the “on” state (i.e., Δn_{Si} = 0) are −8, −7, and −5.5 dB for the modulators with the SiO_{2} width of 2, 5 and 10 nm, respectively. The insertion loss is contributed by the splitter loss, the propagation loss in the plasmonic slot waveguide, and the combiner loss. The splitter/combiner loss estimated from Fig. 8(a) is ~0.8-1.0 dB per facet and the propagation losses estimated from Fig. 4(b) are ~6.1, ~5.2, and ~4.2 dB for the MOS-type plasmonic slot waveguides with W_{SiO2} of 2, 5 and 10 nm, respectively. The sum of these losses is in good agreement with the insertion loss read from Fig. 11.

The extinction ratio at the “off” state is ~7.3 dB at Δn_{Si} = −0.22 for the 2-nm SiO_{2} modulator, ~7.1 dB at Δn_{Si} = −0.29 for the 5-nm SiO_{2} modulator, and ~10.0 dB at Δn_{Si} = −0.39 for the 10-nm SiO_{2} modulator. The *d*n_{eff}/*d*n_{Si} values for these three MOS-type plasmonic slot waveguides read from Fig. 4(a) are ~1.17, ~0.88, and ~0.66, respectively. The corresponding Δn_{eff} values for these three waveguides are all calculated to be ~-0.258. We can see that the simulation result obeys the general equation of

_{0}= 1.55 µm and L

_{π}= 3 µm is the waveguide length for π phase shift. Figure 12 shows one example of the field distributions in the modulator at “on” and “off” states which has a Ag-SiO

_{2}(2 nm)-Si(50 nm)-Ag phase shifter. We can see that the waves at the end of two MOS-type plasmonic slot waveguides have the same phase at the “on” state while they have a π phase shift at the “off” state (indicated by the colors). The remaining output power at the “off” state can be attributed to the variation of L

_{p}with Δn

_{Si}, as depicted in Fig. 4(b). It makes the wave amplitudes after propagating through these two plasmonic slot waveguides are no longer exactly equal. The asymmetric splitter showed in Fig. 9 can be utilized to compensate the effect. Then, a zero output power can be achieved theoretically.

The modulator also works if Ag is replaced by Cu or Al. The Cu-SiO_{2}(2 nm)-Si(50 nm)-Cu modulator exhibits a slightly large insertion loss of ~–9 dB and similar extinction property as the Ag counterpart. It indicates that Cu is also a suitable candidate for our nanoplasmonic modulator. However, the Al-SiO_{2}(2 nm)-Si(50 nm)-Al modulator has relatively poorer performance as compared to the Ag and Cu counterparts. The insertion loss is ~11 dB and the required Δn_{Si} for extinction of ~5.5 dB is −0.26. It indicates that Al is not a good metal for our plasmonic modulator, most probably because of its much large imaginary part of permittivity at wavelength around 1.55 µm as compared with the other two metals [36].

The operating mechanism of our modulator looks like the conventional Si MZI modulator [37]. However, as the abovementioned, the MOS-type plasmonic slot waveguides in our modulator support only a plasmonic mode. Therefore, it is the plasmonic mode, not the optical mode, is modulated in our modulators. Here, we demonstrate for the first time by simulation that (1) the optical mode in the Si dielectric waveguide can be effectively converted to the plasmonic mode in the plasmonic slot waveguide through a simple V-shape splitter; (2) the phase of the plasmonic mode in the MOS-type plasmonic slot waveguide can be substantially modified through the n_{Si} variation; (3) two in-phase plasmonic waves can interfere constructively and be converted to the optical mode in the Si waveguide through a simple Λ-shape combiner, and (4) two anti-phase plasmonic waves interfere destructively at the combiner to extinguish the light.

## 6. Electrical properties of the MOS-type plasmonic slot waveguides

In the above analysis, we arbitrarily assume a uniform Si real index variation in the MOS-type plasmonic slot waveguide. However, the free carrier variation in the Si layer of a real MOS capacitor is not uniform, so that the Si refractive index variation is also not uniform through the free carrier plasma dispersion effect. Moreover, both the real and imaginary parts of the Si index are simultaneously modified. Here, the semiconductor device simulation software MEDICI is used to calculate the free carrier distributions in MOS capacitors under various gate voltages. The modified local density approximation method [38] and Fermi-Dirac statistics of free carriers near the SiO_{2}/Si interface are taken into account. The Si layer in our MOS capacitors is assumed to be n-type doped with the uniform doping level of 5 × 10^{18} cm^{−3}. The build-in carrier concentration dependent mobility in MEDICI and the Shockley-Read-Hall recombination model are used during the electrical simulations.

Figure 13
shows the free electron distributions in the Ag-SiO_{2}(2 nm)-Si(50 nm)-Ag MOS capacitor under an applied voltage ranging from 0 to 6 V. At the 0 V bias, the Si layer near the SiO_{2}/Si interface is depleted. The free electrons are accumulated near the SiO_{2}/Si interface when a positive gate voltage is applied. The electron concentration within a narrow region near the SiO_{2}/Si interface increases quickly with the gate voltage increasing. A very high electron concentration (e.g., > 10^{21} cm^{−3}) can be achieved in this region at a large voltage. For the carrier concentration less than 10^{20} cm^{−3}, the real refractive index variation (Δn_{Si}) and the absorption coefficient variation (Δα_{Si}) of Si at λ_{0} = 1.55 µm as a function of the carrier concentration can be expressed as [39]:

^{20}cm

^{−3}, Eq. (3) may be no longer valid. Instead, the Drude model should be utilized to assess the complex permittivity of silicon as [40]:

_{0}, m*, ω, and τ are the free carrier concentration, electronic charge, vacuum permittivity, electron effective mass, angular frequency of light, and relaxation time, respectively. ε

_{∞}= 11.7 is the Si relative permittivity at infinitely high frequency. The inset of Fig. 13 shows n

_{Si}as a function of the electron concentration calculated from Eq. (3) and Eq. (4). At the N <10

^{20}cm

^{−3}region, both models give a similar n

_{Si}. However, at the N > 10

^{20}cm

^{−3}region, n

_{Si}calculated from Eq. (4) is substantially smaller than that calculated from Eq. (3), and the deviation becomes larger with N further increasing. Based on the Drude model, n

_{Si}will be smaller than n

_{SiO2}(i.e., 1.445) when N > ~1.2 × 10

^{21}cm

^{−3}. In this study, the Drude model is used to translate the electron concentration distributions in the MOS-type plasmonic slot waveguides obtained from the MEDICI simulation to the n

_{Si}distributions for the optical simulation.

To evaluate the voltage induced n_{eff} modification in the Ag-SiO_{2}-Si(50 nm)-Ag plasmonic slot waveguide using FullWAVE from RSOFT, the electron distribution, which is then translated to the complex n_{Si} distribution, is approximated by a step function with 8 discrete layers, namely, 0-0.2, 0.2-0.5, 0.5-1, 1-2, 2-5, 5-10, 10-40, and 40-50 nm, respectively. To capture the field change in the 0.2-nm Si layer, the un-uniform grid size is set to 0.5 nm at the bulk and 0.1 nm at the interface, and the minimum grid number in each layer is 2. Figure 14
shows n_{eff} modification (Δn_{eff}) of Ag-SiO_{2}(W_{SiO2})-Si(50 nm)-Ag MOS-type plasmonic slot waveguides as a function of the applied voltage for W_{SiO2} of 2, 3, 4, and 5 nm, respectively. Δn_{eff} increases slowly with increasing voltage at the small voltage region and then it increases very quickly when a sufficient large voltage is applied. This can be explained that when the electron concentration near the SiO_{2}/Si interface is sufficiently large (e.g, > ~1.2 × 10^{21} cm^{−3}), the real part of n_{Si} becomes smaller than the neighboring n_{SiO2}, then, the SPP modal power in the plasmonic slot waveguide will be concentrated in this low-index region, like in the case of Fig. 3(c), thus the contribution of this very narrow layer to the overall effective modal index is dramatically enhanced. To reach the π-phase shift in the 3-μm long waveguide phase shifter (the required Δn_{eff} is −0.258, as calculated from Eq. (2), the required switching voltages (V_{π}) are ~5.6, ~8.1, ~10.4, and ~12.9 V for the Ag-SiO_{2}(W_{SiO2})-Si(50 nm)-Ag phase shifters with the gate SiO_{2} thicknesses of 2, 3, 4, and 5 nm, respectively. The larger gate oxide thickness requires a larger V_{π} because (1) a larger voltage is required to accumulate a certain electron concentration near the SiO_{2}/Si interface for a MOS capacitor with thicker gate SiO_{2}; and (2) a larger Δn_{Si} is required to reach a certain Δn_{eff} for the MOS-type metal-SiO_{2}(W_{SiO2})-Si-metal plasmonic slot waveguide with larger W_{SiO2} because the value of *d*n_{eff}/*d*n_{Si} deceases with increasing W_{SiO2}, as revealed in Fig. 5(c). We can see that the required V_{π} is already close or larger than the corresponding SiO_{2} breakdown voltage, especially in the thicker SiO_{2} case [41]. This is the main issue of our modulator. Therefore, the major challenge to realize our modulator is to get a high quality ultrathin gate SiO_{2} layer, i.e., with its breakdown voltage larger than V_{π}. In the modern nanoscale CMOS technology [31], this requirement could be achievable by an improved processing technology. V_{π} can be reduced by extending the length of the phase shifter, but compensated by the insertion loss increase, thus it is not a good solution.

One possible approach to solve, or to alleviate at least, this problem is to use a high-κ dielectric, such as HfO_{2}, to replace the gate SiO_{2}. The reasons are (1) high-κ dielectrics usually have a larger refractive index than SiO_{2}, e.g., HfO_{2} has an index of ~2.32 [42], thus the required electron concentration in Si (for n_{Si} to equal the HfO_{2} refractive index) is reduced; and (2) high-κ dielectrics have a smaller equivalent oxide thickness (EOT), thus requiring a smaller voltage than the corresponding case of SiO_{2} to reach the necessary electron concentration in Si. Generally, a desirable high-κ dielectric to be adopted in our modulator should have large real refractive index, large dielectric constant (κ-value), small optical absorption coefficient, large breakdown voltage, and is Si-CMOS compatible. So far, very few data have been reported in literature about the introduction of high-κ dielectric materials in the optical devices. In our group, the relevant studies are still on-going.

For transient state simulation using MEDICI, the gate voltage is increased from 0 to 5 V for the Ag-SiO_{2}(2 nm)-Si(50 nm)-Ag phase shifter and it is increased from 0 to 12 V for the Ag-SiO_{2}(5 nm)-Si(50 nm)-Ag phase shift. The voltage drops to 0 V after 1000 ps. The ramp and fall times of the gate voltage are set to 0.05 ps. The electron concentration near the SiO_{2}/Si interface is monitored as a function of time. The results are shown in Fig. 15
. Rise time (t_{r}) is defined as the time for the electron concentration to increase from 10% to 90%, and fall time (t_{f}) is defined as the time for electron concentration to decrease from 90% to 10%. The t_{r} and t_{f} for the Ag-SiO_{2}(2 nm)-Si(50 nm)-Ag phase shifter is read to be ~1.09 ps and ~0.71 ps, respectively. The modulation speed (f_{max}) in GHz is defined as the inverse of the sum of these two times:

Therefore, the Ag-SiO_{2}(2 nm)-Si(50 nm)-Ag modulator can achieve a modulation speed as high as ~500 GHz. The modulator with thicker SiO_{2} exhibits even higher speed because of its smaller gate capacitance. The high speed of our modulator can be attributed to the horizontal Ag-SiO_{2}-Si-Ag configuration with the very narrow Si width. Because our MOS-type plasmonic waveguide phase shifter works between depletion and accumulation of the majority carriers (electrons here) near the SiO_{2}/Si interface, the accumulated electrons near the SiO_{2}/Si are injected from and swept to the opposite cathode electrode through the bulk Si upon the applied voltage variation (i.e., the slow carrier generation/recombination process is not involved). For our horizontal Ag-SiO_{2}-Si-Ag configuration, the distance for which electrons need to transport is only 50 nm, thus leading to the very high modulation speed of hundreds of GHz. For comparison, Moselund et al calculated for their gate-all-around modulator that the modulation speed can be tens of GHz if the distance for which carriers need to transport is ~1 µm or less [43], in agreement with our result if scaled to the same distance. The other modulation speed limit is the RC delay, which is defined as

_{2}(2nm)-Si(50nm)-Ag capacitor with a typical thickness of 0.22 µm and length of 3 µm, C is calculated to ~11.4 fF. The total load resistance depends on the detailed layout of the modulator and fabrication processes. A typical value of the load resistance is ~15 Ω. Then, f

_{max}is calculated to be ~900 GHz. It indicates that the speed of our modulator is still limited by the carrier transport time.

## 7. Conclusions

In summary, a novel Si nanoplasmonic MZI modulator is proposed and analyzed, including a MOS-type plasmonic slot waveguide for phase shifting, a simple V-shape splitter to deliver light from a conventional Si dielectric waveguide to two plasmonic slot waveguides. The properties of the MOS-type plasmonic slot waveguides and the splitter are systematically investigated using 2-D FDTD simulation, from which the modulator’s parameters are optimized. Numeric simulation shows that the proposed nanoplasmonic modulator with a 2-nm gate oxide has the modulation speed of ~500 GHz, the total on-chip insertion loss of ~8 dB, and the static extinction ratio of ~7.6 dB at an applied voltage of ~5.6 V. The switching voltage may be reduced if the gate SiO_{2} is replaced by a suitable high-κ gate dielectric.

## References and links

**1. **M. Dragoman and D. Dragoman, “Plasmonics: applications to nanoscale terahertz and optical devices,” Prog. Quantum Electron. **32**(1), 1–41 (2008). [CrossRef]

**2. **S. A. Maier, *Plasmonics: Fundamentals and Applications* (Springer Science + Business Media LLC, 2007).

**3. **M. L. Brongersma and P. G. Kik, *Surface Plasmon Nanophotonics* (Springer Science + Business Media LLC, 2007).

**4. **S. I. Bozhevolnyi, *Plasmonic Nanoguides and Circuits* (Pan Stanford Publishing, 2009).

**5. **J. A. Dionne, L. A. Sweatlock, H. A. Atwater, and A. Polman, “Plasmon slot waveguides: towards chip-scale propagation with subwavelength-scale localization,” Phys. Rev. B **73**(3), 035407 (2006). [CrossRef]

**6. **R. F. Oulton, G. Bartal, D. F. P. Pile, and X. Zhang, “Confinement and propagation characteristics of subwavelength plasmonic modes,” N. J. Phys. **10**(10), 105018 (2008). [CrossRef]

**7. **S. I. Bozhevolnyi, V. S. Volkov, E. Devaux, J. Y. Laluet, and T. W. Ebbesen, “Channel plasmon subwavelength waveguide components including interferometers and ring resonators,” Nature **440**(7083), 508–511 (2006). [CrossRef] [PubMed]

**8. **B. Min, E. Ostby, V. Sorger, E. Ulin-Avila, L. Yang, X. Zhang, and K. Vahala, “High-Q surface-plasmon-polariton whispering-gallery microcavity,” Nature **457**(7228), 455–458 (2009). [CrossRef] [PubMed]

**9. **J. Tian, S. Yu, W. Yan, and M. Qiu, “Broadband high-efficiency surface-plasmon-polariton coupler with silicon-metal interface,” Appl. Phys. Lett. **95**(1), 013504 (2009). [CrossRef]

**10. **L. Chen, J. Shakya, and M. Lipson, “Subwavelength confinement in an integrated metal slot waveguide on silicon,” Opt. Lett. **31**(14), 2133–2135 (2006). [CrossRef] [PubMed]

**11. **R. A. Wahsheh, Z. Lu, and M. A. G. Abushagur, “Nanoplasmonic couplers and splitters,” Opt. Express **17**(21), 19033–19040 (2009). [CrossRef]

**12. **P. Mühlschlegel, H. J. Eisler, O. J. Martin, B. Hecht, and D. W. Pohl, “Resonant optical antennas,” Science **308**(5728), 1607–1609 (2005). [CrossRef] [PubMed]

**13. **A. Hryciw, Y. C. Jun, and M. L. Brongersma, “Plasmonics: Electrifying plasmonics on silicon,” Nat. Mater. **9**(1), 3–4 (2010). [CrossRef]

**14. **T. Ishi, J. Fujikata, K. Makita, Y. Baba, and K. Ohashi, “Si nano-photodiode with a surface plasmon antenna,” Jpn. J. Appl. Phys. **44**(12), L364–L366 (2005). [CrossRef]

**15. **J. A. Dionne, K. Diest, L. A. Sweatlock, and H. A. Atwater, “PlasMOStor: a metal-oxide-Si field effect plasmonic modulator,” Nano Lett. **9**(2), 897–902 (2009). [CrossRef] [PubMed]

**16. **W. Cai, J. S. White, and M. L. Brongersma, “Compact, high-speed and power-efficient electrooptic plasmonic modulators,” Nano Lett. **9**(12), 4403–4411 (2009). [CrossRef] [PubMed]

**17. **D. Marris-Morini, L. Vivien, G. Rasigade, J. M. Fedeli, E. Cassan, X. L. Roux, P. Crozat, S. Maine, A. Lupu, P. Lyan, P. Rivallin, M. Halbwax, and S. Laval, “Recent progress in high-speed silicon-based optical modulators,” Proc. IEEE **97**(7), 1199–1215 (2009). [CrossRef]

**18. **K. F. MacDonald and N. I. Zheludev, “Active plasmonics: current status,” Laser Photon. Rev. **4**(4), 562–567 (2010). [CrossRef]

**19. **C. Min and G. Veronis, “Absorption switches in metal-dielectric-metal plasmonic waveguides,” Opt. Express **17**(13), 10757–10766 (2009). [CrossRef] [PubMed]

**20. **S. W. Liu and M. Xiao, “Electro-optic switch in ferroelectric thin films mediated by surface plasmons,” Appl. Phys. Lett. **88**(14), 143512 (2006). [CrossRef]

**21. **P. R. Evans, G. A. Wurtz, W. R. Hendren, R. Atkinson, W. Dickson, A. V. Zayats, and R. J. Pollard, “Electrically switchable nonreciprocal transmission of plasmonic nanorods with liquid crystal,” Appl. Phys. Lett. **91**(4), 043101 (2007). [CrossRef]

**22. **T. Nikolajsen, K. Leosson, and S. I. Bozhevolnyi, “Surface Plasmon polariton based modulators and switches operating at telecom wavelengths,” Appl. Phys. Lett. **85**(24), 5833–5835 (2004). [CrossRef]

**23. **K. J. Chau, S. E. Irvine, and A. Y. Elezzabi, “A gigahertz surface magneto-plasmon optical modulator,” IEEE J. Quantum Electron. **40**(5), 571–579 (2004). [CrossRef]

**24. **D. Gérard, V. Laude, B. Sadani, A. Khelif, D. Van Labeke, and B. Guizal, “Modulation of the extraordinary optical transmission by surface acoustic waves,” Phys. Rev. B **76**(23), 235427 (2007). [CrossRef]

**25. **K. F. MacDonald, Z. L. Samson, M. I. Stockman, and N. I. Zheludev, “Ultrafast active plasmonics,” Nat. Photonics **3**(1), 55–58 (2009). [CrossRef]

**26. **X. J. Huang, W. C. Lee, C. Kuo, D. Hisamoto, L. L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T. J. King, J. Bokor, and C. M. Hu, “Sub-50nm p-channel FinFET,” IEEE Trans. Electron. Dev. **48**(5), 880–886 (2001). [CrossRef]

**28. **G. Veronis and S. Fan, “Theoretical investigation of compact couplers between dielectric slab waveguides and two-dimensional metal-dielectric-metal plasmonic waveguides,” Opt. Express **15**(3), 1211–1221 (2007). [CrossRef] [PubMed]

**29. **R. Salvador, A. Martinez, C. Garcia-Meca, R. Ortuno, and J. Marti, “Analysis of hybrid dielectric plasmonic waveguides,” IEEE J. Sel. Top. Quantum Electron. **14**(6), 1496–1501 (2008). [CrossRef]

**30. **R. F. Oulton, V. J. Sorger, D. A. Genov, D. F. P. Pile, and X. Zhang, “A hybrid plasmonic waveguide for subwavelength confinement and long-rang propagation,” Nat. Photonics **2**(8), 496–500 (2008). [CrossRef]

**31. **S. Deleonibus, *Electronic device architectures for the nano-CMOS era: from ultimate CMOS scaling to beyond CMOS devices* (Pan Stanford Publishing, 2009).

**32. **J. Takahara, S. Yamagishi, A. Morimoto, and T. Kobayashi, “Nanostructure optical phase modulator and detector using surface plasmon polariton,” Pacific Rim Conf. on Lasers and Electro-optics 1997, 42–42.

**33. **S. I. Bozhevolnyi and J. Jung, “Scaling for gap plasmon based waveguides,” Opt. Express **16**(4), 2676–2684 (2008). [CrossRef] [PubMed]

**34. **N.-N. Feng, M. L. Brongersma, and L. Dal Negro, “Metal-dielectric slot waveguide structures for the propagation of surface plasmon polaritons at 1.55 µm,” IEEE J. Quantum Electron. **43**(6), 479–485 (2007). [CrossRef]

**35. **G. Veronis and S. Fan, “Modes of subwavelength plasmonic slot waveguides,” J. Lightwave Technol. **25**(9), 25112521 (2007). [CrossRef]

**36. **D. Palik, *Handbook of Optical Constants of Solid* (Academic, New York, 1985).

**37. **A. Liu, R. Jones, L. Liao, D. Samara-Rubio, D. Rubin, O. Cohen, R. Nicolaescu, and M. Paniccia, “A high-speed silicon optical modulator based on a metal-oxide-semiconductor capacitor,” Nature **427**(6975), 615–618 (2004). [CrossRef] [PubMed]

**38. **J. Sune, P. Olivo, and B. Ricco, “Quantum-mechanical modeling of accumulation layers in MOS structure” IEEE Trans. Electron. Dev. **39**(7), 1732–1739 (1992). [CrossRef]

**39. **R. A. Soref and B. R. Bennett, “Kramers-Kronig analysis of electro-optical switching in silicon,” Proc. SPIE **704**, 32–37 (1986).

**40. **R. Soref, R. E. Peale, and W. Buchwald, “Longwave plasmonics on doped silicon and silicides,” Opt. Express **16**(9), 6507–6514 (2008). [CrossRef] [PubMed]

**41. **H. S. Momose, S. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto, Y. Katsumata, and H. Iwai, ““Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFET’s: uniformity, reliability, and dopant penetration of the gate oxide,” IEEE Tran. Electron. Dev. **45**(3), 691–700 (1998). [CrossRef]

**42. **S. Hall, O. Buiu, I. Z. Mitrovic, Y. Lu, and W. M. Davey, “Review and perspective of high-κ dielectrics on silicon,” J. Telecommun. Info. Technol. **2**, 33–43 (2007).

**43. **K. E. Moselund, P. Dainesi, M. Declercq, M. Bopp, P. Coronel, T. Skotnicki, and A. K. Ionecu, ““Compact gate-all-around silicon light modulator for ultra high speed operation”, Sensor. Actuat,” Adv. Phys. **130**, 220–227 (2006).