A novel scheme for an ultrahigh-speed all-optical half adder based on four-wave mixing (FWM) in semiconductor optical amplifiers (SOAs) is proposed. This scheme is free of pattern effect, due to using the polarization-shift-keying (PolSK) modulation format. By numerical simulation, the output power level of logic “1” dependence on the operating conditions, such as two input signal powers, injection current, and input signal wavelength, are investigated in detail using the broad-band model of this all-optical half adder.
©2006 Optical Society of America
High-speed all-optical logic gates are crucial elements in future high-speed optical networks to perform optical signal processing functions, e.g., addressing, demultiplexing, regeneration and switching. Many approaches have been proposed to achieve all-optical logic functions, based on the nonlinear effects in semiconductor material, in optical fibers or in waveguides. In particular, all-optical logic gates based on the nonlinear effects in semiconductor optical amplifiers (SOAs), such as cross-gain modulation (XGM), cross-phase modulation (XPM), four-wave mixing (FWM), and cross-polarization modulation, are promising due to SOA’s high gain in the optical power, strong change of the refractive index and potential for photonic integration .
The half adder is a basis for the enhanced complex processing circuits including a full adder, a binary decoder, and a binary counter. So far, the half adders are realized using terahertz optical asymmetric demultiplexer (TOAD) , SOAs [3, 4], ultrafast nonlinear interferometers (UNI) , and using a PPLN waveguide and an SOA .
In this paper, a novel scheme for an ultrahigh-speed all-optical half adder based on FWM in SOA is proposed. The polarization-shift-keying (PolSK) modulation format is used in this scheme. Many studies on the PolSK modulation format have been carried out [7–11] due to its unique virtues. Extinction ratio and signal to noise ratio using PolSK modulation are superior to using intensity modulation . PolSK modulation is less sensitive to phase noise of the transmitting lasers in comparison with other coherent transmission schemes . Due to the constant intensity nature of the signal, pattern-dependent degradation can be reduced in this SOA-based device . Moreover, since the FWM effect is used, this scheme can provide ultrafast operation. The effects of two input signal powers, injection current, and input signal wavelength on the crucial parameter of half adder, the output power level of logic “1”, are investigated by numerical simulation in this paper.
2. Operation principle
The half adder is a combinational optical logic unit utilizing two logic functions SUM and CARRY. The truth table for the half adder is shown in Table 1. In fact, logic SUM and logic CARRY exactly coincide with the XOR gate and the AND gate. So the all-optical XOR and AND gates should be employed to implement the half adder. The logic diagram of the half adder is shown in Fig. 1.
Figure 2 shows the schematic diagram of the proposed all-optical half adder. To implement the all-optical half adder, the FWM effects for PolSK signals in two SOAs are used. In PolSK encoding, a logical “1” is associated with a given linear polarization state and a “0” with the orthogonal state. Two strong PolSK signals (S1 and S2) are split using optical coupler (OC) 1 and OC2, respectively. A polarization controller (PC) is used to control the relative polarization state between two signals. After applying a quarter-wave plate in one arm of signal 2 to produce a 90° polarization rotation, the split signals are across coupled into two SOAs, in which the FWM effects occur. It is well known that the FWM effect in an SOA only arises from beating between the same polarizations components of two input signals. Consequently, the generated FWM components (the conjugate signal and the satellite signal) possess the same polarization state as two input signals. In the upper SOA, when two signals are both logic “1”, the resulting intensity and polarization state of the conjugate signal can be obtained. By filtering the conjugate signal and isolating its two polarization components using tunable filter (TF) 1 and polarization beam splitter (PBS) respectively, AND gate can be realized (in fact, NOR gate can be simultaneously obtained from the other PBS output). In the lower SOA, the conjugate signal is generated by FWM between S1 and S2(rotated 90° polarization state). An optical XOR gate can be obtained by directly detecting the intensity of conjugate signal, as shown in Fig. 2. Thus logic SUM and CARRY are simultaneously implemented to realize all-optical half adder.
In our simulations, we assume the used SOAs are polarization independent. SOA is divided into n subsections along the longitudinal direction. When n is sufficiently large, the carrier density in each subsection is considered uniform. The traveling wave equations of two signals, conjugate signal, and satellite signal in subsection i can be expressed as [12,13]
where A is the normalized slowly varying envelope of the light field, is the total optical power inside i subsection, Γ is mode confinement factor, α is the linewidth enhancement factor, αl is the loss of SOA, Psat is saturation power, the coefficients ηjj′, j≠j′, j=s1, s2,c,sat represent the nonlinear interactions among the mixing waves .
gj,i(N) is the material gain coefficient of the SOA and can be expressed as 
where N is the carrier density, e is the electron charge, h is Planck constant, ε 0 is the vacuum permittivity, m 0 is the free-electron mass, mc is the conduction band electron mass, mhh is the effective mass of a heavy hole in the valence band, c is the speed of light in vacuum, ng is the refractive index, Δ is the spin-orbit splitting, |M|2 is momentum matrix element, Eg is the band gap energy, fc and fv are the Fermi-Dirac distributions for the conduction and valence bands, respectively.
To calculate the amplified spontaneous emission (ASE) spectrum, the whole spontaneous emission spectrum is divided into m segments. The traveling wave equations for the ASE spectrum in the wavelength between λ j-1 and λj can be expressed as 
where Wj,i(z,t) is the power spectrum density, gj,i′ is the stimulated emission rate per unit length of the SOA and is given by
The carrier density in subsection i can be described by the rate equation
where I is the injection current, wdL is the volume of the active region, c 1 is the Nonradiative recombination coefficient, c 2 is the bimolecular recombination coefficient, c 3 is the Auger recombination coefficient. Gj,i=exp(ḡj,iΔl) is the gain of the subsection i. The third and fourth terms on the right-hand side are carrier consumption induced by the stimulated emission for the signals, conjugate signal, satellite signal, and the ASE.
4. Simulation and results
The parameters used in our simulation are summarized in Table 2.
In the simulations, the return-to-zero (RZ)-PolSK bit sequences have been used for two input signals at repetition rates of 40Gb/s with a pulse duration equal to T/4, where T is the repetition period. This scheme for all-optical half adder makes no matter to apply to the higher data rate. The peak powers of two input signals are both 15mW. The wavelengths are 1550nm and 1551nm. The correspondence wavelengths of the conjugate and satellite signals are 1549nm and 1552nm, respectively. The other parameters are reported in .
Figure 3 shows the simulation results of this kind of all-optical half adder. Figure 3(a) and 3(b) are the intensity waveforms for the given polarization states of signal 1 and signal 2, respectively. The corresponding RZ-PolSK bit sequences are “11001011000101011001” and “01110000111110110010” for two input signals. The demodulated bit sequences in Fig. 3(c) and 3(d) are “01000000000100010000” and “10111011111011101011”. They are just the AND and the XOR between two input signals. The logic SUM and logic CARRY of half adder exactly coincide with the XOR gate and the AND gate. Therefore all-optical half adder can be achieved using this scheme.
From the output waveforms of this proposed all-optical half adder, we can find that, although two SOAs are in deep saturation region, due to the constant envelope of the PolSK signal, pattern effect almost can’t be observed.
In a half adder, the output power level of logic “1” is a crucial parameter for evaluating the logic performance. Improving this parameter is essential for a low bit-error rate operation of half adder. As mentioned earlier, in this scheme, the AND and XOR functions are realized by filtering two conjugate signals of FWM respectively. So the powers of two input signals need not be equal. Thus, the effects of the input signal powers on the output power level of logic “1” are investigated by numerical simulation.
Figure 4 shows the output power level of logic “1” of the AND and XOR logic gates as a function of input signal 2 power, whilst keeping all other operating parameters constant. The conjugate signal power is changed by interaction between input powers and gain saturation. With increasing the input signal 2 powers, the conjugate signal powers are increased, because it is proportional to gain and the power of signal 2. However, with further increase of signal 2 power, the conjugate signal power is decreased due to SOA being in strong gain saturation region. So the output power level of logic “1” of the AND and XOR logic gates first increases then decreases as the input signal 2 increases.
Figure 5 shows the output power level of logic “1” of the AND and XOR logic gates versus input signal 1 power. It is clearly seen that, with the signal 1 power increasing from 2mW to 30mW, the output power level of logic “1” of half adder increases first quickly then slowly, but not decreases. This is attributed to the fact that the output power of the conjugate signal is proportional to the square of signal 1 power, whereas proportional to the signal 2 power. So the effect of signal 1 on conjugate signals is larger than signal 2. Therefore, when the signal 2 power reaches 30mW, although SOA is already in strong gain saturation region, the output power level of logic “1” is still not decreased. In our simulation, when the peak power of input signal 1 exceeds 80mW, the output power level of logic “1” begins to decrease. But, in general, too large input signal power cannot be used.
Figure 6 shows the output power level of logic “1” of AND gate and XOR gate as a function of injection current. The rise of injection current, namely increase of the carrier density, induces the larger gain of SOA. So FWM efficiency is improved. As a result, the output powers of the logic “1” are increased as the injection current rises. However, the current can’t be increased as high as possible because the heat generated due to high injection current and the thermal-related degradation will limit the lever of the injection current that can be applied to the device.
The effect of the input signal 2 wavelength positions relative to the input signal 1 wavelength is also investigated. In our simulations, the input signal 1 wavelength is 1550nm. Figure 7 shows the output power level of logic “1” of AND gate and XOR gate as a function of signal 2 wavelength. It can be seen that the output powers of the logic “1” is decreased with the increase of the detuning frequency. This is mostly because the frequency response of nonlinear process deceases as the detuning frequency increases.
A novel ultrahigh-speed half adder for PloSK modulator format based on FWM in SOAs is proposed. By numerical simulation, the output power level of logic “1”, a crucial parameter of the all-optical half adder, is investigated. The results indicate that, due to using the PolSK modulation format, pattern effect can not existent. In general power range, higher input signal 1 power can increase the output power level of logic “1”. As the input signal 2 increases, the output power level of logic “1” of this kind of half adder first increases then decreases, so the input signal 2 power should be optimized. High injection current improves the output power level of logic “1”. However it can’t be too high. The output power level of logic “1” is decreased as the frequency detuning between two input signals. Therefore the frequency detuning should be set small.
Related researches are supported by National Natural Science Foundation (Grant No.60407001) the Program for New Century Excellent Talents in University of Ministry of Education (NCET-04-0715), and the National Science Foundation for Post-doctoral Scientists of China.
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