Abstract

We experimentally demonstrate the first all-optical Ternary-Content Addressable Memory (T-CAM) cell that operates at 10Gb/s and comprises two monolithically integrated InP Flip-Flops (FF) and a SOA-MZI optical XOR gate. The two FFs are responsible for storing the data bit and the ternary state ‘X’, respectively, with the XOR gate used for comparing the stored FF-data and the search bit. The experimental results reveal error-free operation at 10Gb/s for both Write and Ternary Content Addressing of the T-CAM cell, indicating that the proposed optical T-CAM cell could in principle lead to all-optical T-CAM-based Address Look-up memory architectures for high-end routing applications.

© 2018 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

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References

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  1. C. G. C. Index, “Forecast and Methodology, 2015-2020 White Paper,” (CISCO, 2016).
  2. P. J. Winzer, “Scaling optical fiber networks: Challenges and solutions,” Opt. Photonics News 26(3), 28–35 (2015).
    [Crossref]
  3. N. T. M. Moralis-Pegios, G. Mourgias-Alexandris, K. Vyrsokinos, and N. Pleros “A low-latency high-port count optical switch with optical delay line buffering for disaggregated data centers,” (SPIE).
  4. K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid-State Circuits 41(3), 712–727 (2006).
    [Crossref]
  5. B.-D. Yang and L.-S. Kim, “A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver,” IEEE J. Solid-State Circuits 40(8), 1736–1744 (2005).
    [Crossref]
  6. S. Jeloka, N. Akesh, D. Sylvester, and D. Blaauw, “A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell,” in 2015 Symposium on VLSI Circuits (VLSI Circuits) (IEEE, 2015), pp. C272–C273.
    [Crossref]
  7. K. Nii, T. Amano, N. Watanabe, M. Yamawaki, K. Yoshinaga, M. Wada, and I. Hayashi, “A 28nm 400MHz 4-parallel 1.6 Gsearch/s 80Mb ternary CAM,” in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (IEEE, 2014), pp. 240–241.
  8. I. Arsovski, A. Patil, R. M. Houle, M. T. Fragano, R. Rodriguez, R. Kim, and V. Butler, “1.4 Gsearch/s 2-Mb/mm2\TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,” IEEE J. Solid-State Circuits 53(1), 155–163 (2017).
    [Crossref]
  9. X. Yin, M. Niemier, and X. S. Hu, “Design and benchmarking of ferroelectric fet based tcam,” in 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), (IEEE, 2017), 1444–1449.
  10. A. F. Fonseca, D. L. Willian, T. R. Soares, L. G. Melo, and O. P. V. Neto, “CAM/TCAM—NML:(Ternary) content addressable memory implemented with nanomagnetic logic,” in 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI) (IEEE, 2017), pp. 174–179.
  11. S. Tabassum, F. Parveen, and A. H.-u. Rashid, “Low power high speed Ternary Content Addressable Memory design using 8 MOSFETs and 4 memristors-hybrid structure,” in Electrical and Computer Engineering (ICECE),2014International Conference on, (IEEE, 2014), 168–171.
    [Crossref]
  12. P. Maniotis, D. Fitsios, G. Kanellos, and N. Pleros, “Optical buffering for chip multiprocessors: a 16GHz optical cache memory architecture,” J. Lightwave Technol. 31(24), 4175–4191 (2013).
    [Crossref]
  13. E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
    [Crossref]
  14. S. Pitris, C. Vagionas, G. T. Kanellos, N. Pleros, R. Kisacik, T. Tekin, and R. Broeke, “Monolithically integrated all-optical SOA-based SR Flip-Flop on InP platform,” in 2015 International Conference on Photonics in Switching (PS) (IEEE, 2015), pp. 208–210.
    [Crossref]
  15. D. Fitsios, T. Alexoudi, A. Bazin, P. Monnier, R. Raj, A. Miliou, G. T. Kanellos, N. Pleros, and F. Raineri, “Ultra-compact III‒V-on-Si photonic crystal memory for flip-flop operation at 5 Gb/s,” Opt. Express 24(4), 4270–4277 (2016).
    [Crossref] [PubMed]
  16. G. Berrettini, L. Poti, and A. Bogoni, “Optical dynamic RAM for all-optical digital processing,” IEEE Photonics Technol. Lett. 23(11), 685–687 (2011).
    [Crossref]
  17. S. Pitris, C. Vagionas, P. Maniotis, G. T. Kanellos, and N. Pleros, “An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s,” IEEE Photonics Technol. Lett. 28(16), 1790–1793 (2016).
    [Crossref]
  18. P. Maniotis and N. Pleros, “All-optical ternary-content addressable memory (T-CAM) cell and row architectures for address lookup at 20 Gb/s,” Opt. Quantum Electron. 49(11), 348 (2017).
    [Crossref]
  19. C. Vagionas, P. Maniotis, S. Pitris, A. Miliou, and N. Pleros, “Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations,” Appl. Sci. 7(12), 700 (2017).
    [Crossref]
  20. C. Vagionas, D. Fitsios, K. Vyrsokinos, G. T. Kanellos, A. Miliou, and N. Pleros, “XPM-and XGM-based optical RAM memories: frequency and time domain theoretical analysis,” IEEE J. Quantum Electron. 50(8), 1–15 (2014).
    [Crossref]
  21. C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
    [Crossref]
  22. B. Agrawal and T. Sherwood, “Ternary CAM power and delay model: Extensions and uses,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(5), 554–564 (2008).
    [Crossref]
  23. R. Karam, R. Puri, S. Ghosh, and S. Bhunia, “Emerging Trends in Design and Applications of Memory-Based Computing and CAMs,” IEEE Proceedings, 103, 1311–1330, (2015)
  24. K. He, J. Khalid, A. Gember-Jacobson, S. Das, C. Prakash, A. Akella, L. E. Li, and M. Thottan, “Measuring Control Plane Latency in SDN-enabled Switches,” in Proceedings of ACM Sigcomm (2015)
    [Crossref]

2017 (3)

I. Arsovski, A. Patil, R. M. Houle, M. T. Fragano, R. Rodriguez, R. Kim, and V. Butler, “1.4 Gsearch/s 2-Mb/mm2\TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,” IEEE J. Solid-State Circuits 53(1), 155–163 (2017).
[Crossref]

P. Maniotis and N. Pleros, “All-optical ternary-content addressable memory (T-CAM) cell and row architectures for address lookup at 20 Gb/s,” Opt. Quantum Electron. 49(11), 348 (2017).
[Crossref]

C. Vagionas, P. Maniotis, S. Pitris, A. Miliou, and N. Pleros, “Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations,” Appl. Sci. 7(12), 700 (2017).
[Crossref]

2016 (2)

D. Fitsios, T. Alexoudi, A. Bazin, P. Monnier, R. Raj, A. Miliou, G. T. Kanellos, N. Pleros, and F. Raineri, “Ultra-compact III‒V-on-Si photonic crystal memory for flip-flop operation at 5 Gb/s,” Opt. Express 24(4), 4270–4277 (2016).
[Crossref] [PubMed]

S. Pitris, C. Vagionas, P. Maniotis, G. T. Kanellos, and N. Pleros, “An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s,” IEEE Photonics Technol. Lett. 28(16), 1790–1793 (2016).
[Crossref]

2015 (1)

P. J. Winzer, “Scaling optical fiber networks: Challenges and solutions,” Opt. Photonics News 26(3), 28–35 (2015).
[Crossref]

2014 (2)

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

C. Vagionas, D. Fitsios, K. Vyrsokinos, G. T. Kanellos, A. Miliou, and N. Pleros, “XPM-and XGM-based optical RAM memories: frequency and time domain theoretical analysis,” IEEE J. Quantum Electron. 50(8), 1–15 (2014).
[Crossref]

2013 (2)

C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
[Crossref]

P. Maniotis, D. Fitsios, G. Kanellos, and N. Pleros, “Optical buffering for chip multiprocessors: a 16GHz optical cache memory architecture,” J. Lightwave Technol. 31(24), 4175–4191 (2013).
[Crossref]

2011 (1)

G. Berrettini, L. Poti, and A. Bogoni, “Optical dynamic RAM for all-optical digital processing,” IEEE Photonics Technol. Lett. 23(11), 685–687 (2011).
[Crossref]

2008 (1)

B. Agrawal and T. Sherwood, “Ternary CAM power and delay model: Extensions and uses,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(5), 554–564 (2008).
[Crossref]

2006 (1)

K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid-State Circuits 41(3), 712–727 (2006).
[Crossref]

2005 (1)

B.-D. Yang and L.-S. Kim, “A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver,” IEEE J. Solid-State Circuits 40(8), 1736–1744 (2005).
[Crossref]

Agrawal, B.

B. Agrawal and T. Sherwood, “Ternary CAM power and delay model: Extensions and uses,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(5), 554–564 (2008).
[Crossref]

Akella, A.

K. He, J. Khalid, A. Gember-Jacobson, S. Das, C. Prakash, A. Akella, L. E. Li, and M. Thottan, “Measuring Control Plane Latency in SDN-enabled Switches,” in Proceedings of ACM Sigcomm (2015)
[Crossref]

Akesh, N.

S. Jeloka, N. Akesh, D. Sylvester, and D. Blaauw, “A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell,” in 2015 Symposium on VLSI Circuits (VLSI Circuits) (IEEE, 2015), pp. C272–C273.
[Crossref]

Alexoudi, T.

D. Fitsios, T. Alexoudi, A. Bazin, P. Monnier, R. Raj, A. Miliou, G. T. Kanellos, N. Pleros, and F. Raineri, “Ultra-compact III‒V-on-Si photonic crystal memory for flip-flop operation at 5 Gb/s,” Opt. Express 24(4), 4270–4277 (2016).
[Crossref] [PubMed]

C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
[Crossref]

Arsovski, I.

I. Arsovski, A. Patil, R. M. Houle, M. T. Fragano, R. Rodriguez, R. Kim, and V. Butler, “1.4 Gsearch/s 2-Mb/mm2\TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,” IEEE J. Solid-State Circuits 53(1), 155–163 (2017).
[Crossref]

Bazin, A.

Berrettini, G.

G. Berrettini, L. Poti, and A. Bogoni, “Optical dynamic RAM for all-optical digital processing,” IEEE Photonics Technol. Lett. 23(11), 685–687 (2011).
[Crossref]

Bhunia, S.

R. Karam, R. Puri, S. Ghosh, and S. Bhunia, “Emerging Trends in Design and Applications of Memory-Based Computing and CAMs,” IEEE Proceedings, 103, 1311–1330, (2015)

Blaauw, D.

S. Jeloka, N. Akesh, D. Sylvester, and D. Blaauw, “A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell,” in 2015 Symposium on VLSI Circuits (VLSI Circuits) (IEEE, 2015), pp. C272–C273.
[Crossref]

Bogoni, A.

G. Berrettini, L. Poti, and A. Bogoni, “Optical dynamic RAM for all-optical digital processing,” IEEE Photonics Technol. Lett. 23(11), 685–687 (2011).
[Crossref]

Butler, V.

I. Arsovski, A. Patil, R. M. Houle, M. T. Fragano, R. Rodriguez, R. Kim, and V. Butler, “1.4 Gsearch/s 2-Mb/mm2\TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,” IEEE J. Solid-State Circuits 53(1), 155–163 (2017).
[Crossref]

Dabos, G.

C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
[Crossref]

Das, S.

K. He, J. Khalid, A. Gember-Jacobson, S. Das, C. Prakash, A. Akella, L. E. Li, and M. Thottan, “Measuring Control Plane Latency in SDN-enabled Switches,” in Proceedings of ACM Sigcomm (2015)
[Crossref]

Fitsios, D.

Fonseca, A. F.

A. F. Fonseca, D. L. Willian, T. R. Soares, L. G. Melo, and O. P. V. Neto, “CAM/TCAM—NML:(Ternary) content addressable memory implemented with nanomagnetic logic,” in 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI) (IEEE, 2017), pp. 174–179.

Fragano, M. T.

I. Arsovski, A. Patil, R. M. Houle, M. T. Fragano, R. Rodriguez, R. Kim, and V. Butler, “1.4 Gsearch/s 2-Mb/mm2\TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,” IEEE J. Solid-State Circuits 53(1), 155–163 (2017).
[Crossref]

Gember-Jacobson, A.

K. He, J. Khalid, A. Gember-Jacobson, S. Das, C. Prakash, A. Akella, L. E. Li, and M. Thottan, “Measuring Control Plane Latency in SDN-enabled Switches,” in Proceedings of ACM Sigcomm (2015)
[Crossref]

Ghosh, S.

R. Karam, R. Puri, S. Ghosh, and S. Bhunia, “Emerging Trends in Design and Applications of Memory-Based Computing and CAMs,” IEEE Proceedings, 103, 1311–1330, (2015)

He, K.

K. He, J. Khalid, A. Gember-Jacobson, S. Das, C. Prakash, A. Akella, L. E. Li, and M. Thottan, “Measuring Control Plane Latency in SDN-enabled Switches,” in Proceedings of ACM Sigcomm (2015)
[Crossref]

Houle, R. M.

I. Arsovski, A. Patil, R. M. Houle, M. T. Fragano, R. Rodriguez, R. Kim, and V. Butler, “1.4 Gsearch/s 2-Mb/mm2\TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,” IEEE J. Solid-State Circuits 53(1), 155–163 (2017).
[Crossref]

Index, C. G. C.

C. G. C. Index, “Forecast and Methodology, 2015-2020 White Paper,” (CISCO, 2016).

Jeloka, S.

S. Jeloka, N. Akesh, D. Sylvester, and D. Blaauw, “A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell,” in 2015 Symposium on VLSI Circuits (VLSI Circuits) (IEEE, 2015), pp. C272–C273.
[Crossref]

Kanellos, G.

C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
[Crossref]

P. Maniotis, D. Fitsios, G. Kanellos, and N. Pleros, “Optical buffering for chip multiprocessors: a 16GHz optical cache memory architecture,” J. Lightwave Technol. 31(24), 4175–4191 (2013).
[Crossref]

Kanellos, G. T.

D. Fitsios, T. Alexoudi, A. Bazin, P. Monnier, R. Raj, A. Miliou, G. T. Kanellos, N. Pleros, and F. Raineri, “Ultra-compact III‒V-on-Si photonic crystal memory for flip-flop operation at 5 Gb/s,” Opt. Express 24(4), 4270–4277 (2016).
[Crossref] [PubMed]

S. Pitris, C. Vagionas, P. Maniotis, G. T. Kanellos, and N. Pleros, “An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s,” IEEE Photonics Technol. Lett. 28(16), 1790–1793 (2016).
[Crossref]

C. Vagionas, D. Fitsios, K. Vyrsokinos, G. T. Kanellos, A. Miliou, and N. Pleros, “XPM-and XGM-based optical RAM memories: frequency and time domain theoretical analysis,” IEEE J. Quantum Electron. 50(8), 1–15 (2014).
[Crossref]

Karam, R.

R. Karam, R. Puri, S. Ghosh, and S. Bhunia, “Emerging Trends in Design and Applications of Memory-Based Computing and CAMs,” IEEE Proceedings, 103, 1311–1330, (2015)

Khalid, J.

K. He, J. Khalid, A. Gember-Jacobson, S. Das, C. Prakash, A. Akella, L. E. Li, and M. Thottan, “Measuring Control Plane Latency in SDN-enabled Switches,” in Proceedings of ACM Sigcomm (2015)
[Crossref]

Kim, L.-S.

B.-D. Yang and L.-S. Kim, “A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver,” IEEE J. Solid-State Circuits 40(8), 1736–1744 (2005).
[Crossref]

Kim, R.

I. Arsovski, A. Patil, R. M. Houle, M. T. Fragano, R. Rodriguez, R. Kim, and V. Butler, “1.4 Gsearch/s 2-Mb/mm2\TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,” IEEE J. Solid-State Circuits 53(1), 155–163 (2017).
[Crossref]

Kuramochi, E.

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

Li, L. E.

K. He, J. Khalid, A. Gember-Jacobson, S. Das, C. Prakash, A. Akella, L. E. Li, and M. Thottan, “Measuring Control Plane Latency in SDN-enabled Switches,” in Proceedings of ACM Sigcomm (2015)
[Crossref]

Maniotis, P.

C. Vagionas, P. Maniotis, S. Pitris, A. Miliou, and N. Pleros, “Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations,” Appl. Sci. 7(12), 700 (2017).
[Crossref]

P. Maniotis and N. Pleros, “All-optical ternary-content addressable memory (T-CAM) cell and row architectures for address lookup at 20 Gb/s,” Opt. Quantum Electron. 49(11), 348 (2017).
[Crossref]

S. Pitris, C. Vagionas, P. Maniotis, G. T. Kanellos, and N. Pleros, “An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s,” IEEE Photonics Technol. Lett. 28(16), 1790–1793 (2016).
[Crossref]

P. Maniotis, D. Fitsios, G. Kanellos, and N. Pleros, “Optical buffering for chip multiprocessors: a 16GHz optical cache memory architecture,” J. Lightwave Technol. 31(24), 4175–4191 (2013).
[Crossref]

Markou, S.

C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
[Crossref]

Matsuo, S.

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

Melo, L. G.

A. F. Fonseca, D. L. Willian, T. R. Soares, L. G. Melo, and O. P. V. Neto, “CAM/TCAM—NML:(Ternary) content addressable memory implemented with nanomagnetic logic,” in 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI) (IEEE, 2017), pp. 174–179.

Miliou, A.

C. Vagionas, P. Maniotis, S. Pitris, A. Miliou, and N. Pleros, “Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations,” Appl. Sci. 7(12), 700 (2017).
[Crossref]

D. Fitsios, T. Alexoudi, A. Bazin, P. Monnier, R. Raj, A. Miliou, G. T. Kanellos, N. Pleros, and F. Raineri, “Ultra-compact III‒V-on-Si photonic crystal memory for flip-flop operation at 5 Gb/s,” Opt. Express 24(4), 4270–4277 (2016).
[Crossref] [PubMed]

C. Vagionas, D. Fitsios, K. Vyrsokinos, G. T. Kanellos, A. Miliou, and N. Pleros, “XPM-and XGM-based optical RAM memories: frequency and time domain theoretical analysis,” IEEE J. Quantum Electron. 50(8), 1–15 (2014).
[Crossref]

C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
[Crossref]

Monnier, P.

Moralis-Pegios, N. T. M.

N. T. M. Moralis-Pegios, G. Mourgias-Alexandris, K. Vyrsokinos, and N. Pleros “A low-latency high-port count optical switch with optical delay line buffering for disaggregated data centers,” (SPIE).

Mourgias-Alexandris, G.

N. T. M. Moralis-Pegios, G. Mourgias-Alexandris, K. Vyrsokinos, and N. Pleros “A low-latency high-port count optical switch with optical delay line buffering for disaggregated data centers,” (SPIE).

Neto, O. P. V.

A. F. Fonseca, D. L. Willian, T. R. Soares, L. G. Melo, and O. P. V. Neto, “CAM/TCAM—NML:(Ternary) content addressable memory implemented with nanomagnetic logic,” in 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI) (IEEE, 2017), pp. 174–179.

Notomi, M.

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

Nozaki, K.

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

Pagiamtzis, K.

K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid-State Circuits 41(3), 712–727 (2006).
[Crossref]

Patil, A.

I. Arsovski, A. Patil, R. M. Houle, M. T. Fragano, R. Rodriguez, R. Kim, and V. Butler, “1.4 Gsearch/s 2-Mb/mm2\TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,” IEEE J. Solid-State Circuits 53(1), 155–163 (2017).
[Crossref]

Pitris, S.

C. Vagionas, P. Maniotis, S. Pitris, A. Miliou, and N. Pleros, “Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations,” Appl. Sci. 7(12), 700 (2017).
[Crossref]

S. Pitris, C. Vagionas, P. Maniotis, G. T. Kanellos, and N. Pleros, “An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s,” IEEE Photonics Technol. Lett. 28(16), 1790–1793 (2016).
[Crossref]

Pleros, N.

P. Maniotis and N. Pleros, “All-optical ternary-content addressable memory (T-CAM) cell and row architectures for address lookup at 20 Gb/s,” Opt. Quantum Electron. 49(11), 348 (2017).
[Crossref]

C. Vagionas, P. Maniotis, S. Pitris, A. Miliou, and N. Pleros, “Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations,” Appl. Sci. 7(12), 700 (2017).
[Crossref]

S. Pitris, C. Vagionas, P. Maniotis, G. T. Kanellos, and N. Pleros, “An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s,” IEEE Photonics Technol. Lett. 28(16), 1790–1793 (2016).
[Crossref]

D. Fitsios, T. Alexoudi, A. Bazin, P. Monnier, R. Raj, A. Miliou, G. T. Kanellos, N. Pleros, and F. Raineri, “Ultra-compact III‒V-on-Si photonic crystal memory for flip-flop operation at 5 Gb/s,” Opt. Express 24(4), 4270–4277 (2016).
[Crossref] [PubMed]

C. Vagionas, D. Fitsios, K. Vyrsokinos, G. T. Kanellos, A. Miliou, and N. Pleros, “XPM-and XGM-based optical RAM memories: frequency and time domain theoretical analysis,” IEEE J. Quantum Electron. 50(8), 1–15 (2014).
[Crossref]

C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
[Crossref]

P. Maniotis, D. Fitsios, G. Kanellos, and N. Pleros, “Optical buffering for chip multiprocessors: a 16GHz optical cache memory architecture,” J. Lightwave Technol. 31(24), 4175–4191 (2013).
[Crossref]

N. T. M. Moralis-Pegios, G. Mourgias-Alexandris, K. Vyrsokinos, and N. Pleros “A low-latency high-port count optical switch with optical delay line buffering for disaggregated data centers,” (SPIE).

Poti, L.

G. Berrettini, L. Poti, and A. Bogoni, “Optical dynamic RAM for all-optical digital processing,” IEEE Photonics Technol. Lett. 23(11), 685–687 (2011).
[Crossref]

Prakash, C.

K. He, J. Khalid, A. Gember-Jacobson, S. Das, C. Prakash, A. Akella, L. E. Li, and M. Thottan, “Measuring Control Plane Latency in SDN-enabled Switches,” in Proceedings of ACM Sigcomm (2015)
[Crossref]

Puri, R.

R. Karam, R. Puri, S. Ghosh, and S. Bhunia, “Emerging Trends in Design and Applications of Memory-Based Computing and CAMs,” IEEE Proceedings, 103, 1311–1330, (2015)

Raineri, F.

Raj, R.

Rodriguez, R.

I. Arsovski, A. Patil, R. M. Houle, M. T. Fragano, R. Rodriguez, R. Kim, and V. Butler, “1.4 Gsearch/s 2-Mb/mm2\TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,” IEEE J. Solid-State Circuits 53(1), 155–163 (2017).
[Crossref]

Sato, T.

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

Sheikholeslami, A.

K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid-State Circuits 41(3), 712–727 (2006).
[Crossref]

Sherwood, T.

B. Agrawal and T. Sherwood, “Ternary CAM power and delay model: Extensions and uses,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(5), 554–564 (2008).
[Crossref]

Shinya, A.

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

Soares, T. R.

A. F. Fonseca, D. L. Willian, T. R. Soares, L. G. Melo, and O. P. V. Neto, “CAM/TCAM—NML:(Ternary) content addressable memory implemented with nanomagnetic logic,” in 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI) (IEEE, 2017), pp. 174–179.

Sumikura, H.

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

Sylvester, D.

S. Jeloka, N. Akesh, D. Sylvester, and D. Blaauw, “A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell,” in 2015 Symposium on VLSI Circuits (VLSI Circuits) (IEEE, 2015), pp. C272–C273.
[Crossref]

Takeda, K.

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

Taniyama, H.

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

Thottan, M.

K. He, J. Khalid, A. Gember-Jacobson, S. Das, C. Prakash, A. Akella, L. E. Li, and M. Thottan, “Measuring Control Plane Latency in SDN-enabled Switches,” in Proceedings of ACM Sigcomm (2015)
[Crossref]

Tsiokos, D.

C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
[Crossref]

Vagionas, C.

C. Vagionas, P. Maniotis, S. Pitris, A. Miliou, and N. Pleros, “Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations,” Appl. Sci. 7(12), 700 (2017).
[Crossref]

S. Pitris, C. Vagionas, P. Maniotis, G. T. Kanellos, and N. Pleros, “An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s,” IEEE Photonics Technol. Lett. 28(16), 1790–1793 (2016).
[Crossref]

C. Vagionas, D. Fitsios, K. Vyrsokinos, G. T. Kanellos, A. Miliou, and N. Pleros, “XPM-and XGM-based optical RAM memories: frequency and time domain theoretical analysis,” IEEE J. Quantum Electron. 50(8), 1–15 (2014).
[Crossref]

C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
[Crossref]

Vyrsokinos, K.

C. Vagionas, D. Fitsios, K. Vyrsokinos, G. T. Kanellos, A. Miliou, and N. Pleros, “XPM-and XGM-based optical RAM memories: frequency and time domain theoretical analysis,” IEEE J. Quantum Electron. 50(8), 1–15 (2014).
[Crossref]

N. T. M. Moralis-Pegios, G. Mourgias-Alexandris, K. Vyrsokinos, and N. Pleros “A low-latency high-port count optical switch with optical delay line buffering for disaggregated data centers,” (SPIE).

Willian, D. L.

A. F. Fonseca, D. L. Willian, T. R. Soares, L. G. Melo, and O. P. V. Neto, “CAM/TCAM—NML:(Ternary) content addressable memory implemented with nanomagnetic logic,” in 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI) (IEEE, 2017), pp. 174–179.

Winzer, P. J.

P. J. Winzer, “Scaling optical fiber networks: Challenges and solutions,” Opt. Photonics News 26(3), 28–35 (2015).
[Crossref]

Yang, B.-D.

B.-D. Yang and L.-S. Kim, “A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver,” IEEE J. Solid-State Circuits 40(8), 1736–1744 (2005).
[Crossref]

Appl. Sci. (1)

C. Vagionas, P. Maniotis, S. Pitris, A. Miliou, and N. Pleros, “Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations,” Appl. Sci. 7(12), 700 (2017).
[Crossref]

IEEE J. Quantum Electron. (1)

C. Vagionas, D. Fitsios, K. Vyrsokinos, G. T. Kanellos, A. Miliou, and N. Pleros, “XPM-and XGM-based optical RAM memories: frequency and time domain theoretical analysis,” IEEE J. Quantum Electron. 50(8), 1–15 (2014).
[Crossref]

IEEE J. Solid-State Circuits (3)

K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid-State Circuits 41(3), 712–727 (2006).
[Crossref]

B.-D. Yang and L.-S. Kim, “A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver,” IEEE J. Solid-State Circuits 40(8), 1736–1744 (2005).
[Crossref]

I. Arsovski, A. Patil, R. M. Houle, M. T. Fragano, R. Rodriguez, R. Kim, and V. Butler, “1.4 Gsearch/s 2-Mb/mm2\TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,” IEEE J. Solid-State Circuits 53(1), 155–163 (2017).
[Crossref]

IEEE Photonics J. (1)

C. Vagionas, S. Markou, G. Dabos, T. Alexoudi, D. Tsiokos, A. Miliou, N. Pleros, and G. Kanellos, “Column address selection in optical RAMs with positive and negative logic row access,” IEEE Photonics J. 5(6), 7800410 (2013).
[Crossref]

IEEE Photonics Technol. Lett. (2)

G. Berrettini, L. Poti, and A. Bogoni, “Optical dynamic RAM for all-optical digital processing,” IEEE Photonics Technol. Lett. 23(11), 685–687 (2011).
[Crossref]

S. Pitris, C. Vagionas, P. Maniotis, G. T. Kanellos, and N. Pleros, “An Optical Content Addressable Memory Cell for Address Look-Up at 10 Gb/s,” IEEE Photonics Technol. Lett. 28(16), 1790–1793 (2016).
[Crossref]

IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (1)

B. Agrawal and T. Sherwood, “Ternary CAM power and delay model: Extensions and uses,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(5), 554–564 (2008).
[Crossref]

J. Lightwave Technol. (1)

Nat. Photonics (1)

E. Kuramochi, K. Nozaki, A. Shinya, K. Takeda, T. Sato, S. Matsuo, H. Taniyama, H. Sumikura, and M. Notomi, “Large-scale integration of wavelength-addressable all-optical memories on a photonic crystal chip,” Nat. Photonics 8(6), 474–481 (2014).
[Crossref]

Opt. Express (1)

Opt. Photonics News (1)

P. J. Winzer, “Scaling optical fiber networks: Challenges and solutions,” Opt. Photonics News 26(3), 28–35 (2015).
[Crossref]

Opt. Quantum Electron. (1)

P. Maniotis and N. Pleros, “All-optical ternary-content addressable memory (T-CAM) cell and row architectures for address lookup at 20 Gb/s,” Opt. Quantum Electron. 49(11), 348 (2017).
[Crossref]

Other (10)

C. G. C. Index, “Forecast and Methodology, 2015-2020 White Paper,” (CISCO, 2016).

N. T. M. Moralis-Pegios, G. Mourgias-Alexandris, K. Vyrsokinos, and N. Pleros “A low-latency high-port count optical switch with optical delay line buffering for disaggregated data centers,” (SPIE).

S. Pitris, C. Vagionas, G. T. Kanellos, N. Pleros, R. Kisacik, T. Tekin, and R. Broeke, “Monolithically integrated all-optical SOA-based SR Flip-Flop on InP platform,” in 2015 International Conference on Photonics in Switching (PS) (IEEE, 2015), pp. 208–210.
[Crossref]

X. Yin, M. Niemier, and X. S. Hu, “Design and benchmarking of ferroelectric fet based tcam,” in 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), (IEEE, 2017), 1444–1449.

A. F. Fonseca, D. L. Willian, T. R. Soares, L. G. Melo, and O. P. V. Neto, “CAM/TCAM—NML:(Ternary) content addressable memory implemented with nanomagnetic logic,” in 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI) (IEEE, 2017), pp. 174–179.

S. Tabassum, F. Parveen, and A. H.-u. Rashid, “Low power high speed Ternary Content Addressable Memory design using 8 MOSFETs and 4 memristors-hybrid structure,” in Electrical and Computer Engineering (ICECE),2014International Conference on, (IEEE, 2014), 168–171.
[Crossref]

S. Jeloka, N. Akesh, D. Sylvester, and D. Blaauw, “A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell,” in 2015 Symposium on VLSI Circuits (VLSI Circuits) (IEEE, 2015), pp. C272–C273.
[Crossref]

K. Nii, T. Amano, N. Watanabe, M. Yamawaki, K. Yoshinaga, M. Wada, and I. Hayashi, “A 28nm 400MHz 4-parallel 1.6 Gsearch/s 80Mb ternary CAM,” in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (IEEE, 2014), pp. 240–241.

R. Karam, R. Puri, S. Ghosh, and S. Bhunia, “Emerging Trends in Design and Applications of Memory-Based Computing and CAMs,” IEEE Proceedings, 103, 1311–1330, (2015)

K. He, J. Khalid, A. Gember-Jacobson, S. Das, C. Prakash, A. Akella, L. E. Li, and M. Thottan, “Measuring Control Plane Latency in SDN-enabled Switches,” in Proceedings of ACM Sigcomm (2015)
[Crossref]

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Figures (5)

Fig. 1
Fig. 1 (a) Address Look-up table, (b) Electrical T-CAM cell, (c) All-Optical T-CAM cell, (d) 2 Packaged InP FFs and a close-up view of a single chip
Fig. 2
Fig. 2 Experimental setup of the TFF & XFF write evaluation.
Fig. 3
Fig. 3 (a)-(d) TFF write operation time traces, (e)-(h) XFF write operation time traces, (i) Eye diagrams & BER measurements for both TFF & XFF write operation. Time division in Fig.(a)-(h): 200psec.
Fig. 4
Fig. 4 T-CAM cell experimental setup
Fig. 5
Fig. 5 (a)-(d) T-CAM cell output time traces for TFF = 0, (e)-(h) T-CAM cell output time traces for TFF = 1, (i) BER measurements. Time division in Fig.(a)-(h): 200psec

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