FPGA-based implementation of two-step schedulers for modular optical interconnection networks

Justine Cris Borromeo; Isabella Cerutti; Isabella Cerutti; Piero Castoldi; Rosula Reyes; Nicola Andriolli

doi:10.1364/JOCN.417897

Journal of Optical Communications and Networking
Vol. 13,
Issue 5,
pp. 116-125
(2021)
•https://doi.org/10.1364/JOCN.417897

FPGA-based implementation of two-step schedulers for modular optical interconnection networks

Justine Cris Borromeo, Isabella Cerutti, Piero Castoldi, Rosula Reyes, and Nicola Andriolli

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Justine Cris Borromeo, Isabella Cerutti, Piero Castoldi, Rosula Reyes, and Nicola Andriolli, "FPGA-based implementation of two-step schedulers for modular optical interconnection networks," J. Opt. Commun. Netw. 13, 116-125 (2021)

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Abstract

Optical interconnection networks promise to overcome the limitations of current electronic switching fabrics, enabling higher throughput, lower latency, and lower power consumption. Multi-plane architectures, based on multiple optical switching domains (e.g., space, time, wavelength, orbital angular momentum), are gaining research attention because of their modularity and scalability compared to single-domain switches. An effective scheduler, namely, the two-step scheduler (TSS), has been proposed for multi-plane optical interconnection networks, exploiting their modularity to speed up computations while satisfying the peculiar scheduling constraints. In this paper, a hardware implementation of TSS for modular optical interconnection networks is presented and thoroughly assessed. Both scheduling steps are parallelized with the aim of optimizing the execution time. iSLIP and longest queue first (LQF) scheduling algorithms are exploited in each step, resulting in four TSS configurations that are compared among each other and with classical single-step schedulers (SSSs) in terms of scheduling and hardware performance. TSS outperforms SSS in terms of the number of iterations, maximum operating frequency, worst-case scheduling duration, and required logic resources (i.e., scalability) at the expense of a slight latency penalty. Among all TSS configurations, LQF-based TSS guarantees the lowest scheduling latency, while iSLIP-based TSS minimizes the scheduling duration and the use of field programmable gate array (FPGA) resources.

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	Architecture	Method	Scheduler	Implem.
Andreades and Zervas [13]	Clos	Centralized	Out-of-band	ASIC, FPGA
Andreades et al. [14]	Crossbar	Centralized	Out-of-band	FPGA
LIONS [15]	AWGR	Distributed	In-band	FPGA
OSMOSIS [16]	Crossbar	Centralized	Out-of-band	FPGA
NEPHELE [17]	AWGR	Centralized	Out-of-band	FPGA
PULSE [18]	OCS: wavelength and time slot switching	Centralized	Out-of-band	ASIC
Our previous work [19]	Crossbar	Centralized	Out-of-band	FPGA
This work	Multi-plane	Centralized	Out-of-band	FPGA

TSS	iSLIP-iSLIP	${l o g}_{2} (NM)$
$M$ cards, $N$ ports per card	iSLIP-LQF	${l o g}_{2} (N) + M$
	LQF-iSLIP	$N + {l o g}_{2} (M)$
	LQF-LQF	$N + M$
SSS	iSLIP	${l o g}_{2} (MN)$
$MN$ ports	LQF	$MN$

TSS	iSLIP-iSLIP	$3 {l o g}_{2} (NM) + 4$
$M$ cards, $N$ ports per card	iSLIP-LQF	$3 {l o g}_{2} (N) + M + 4$
	LQF-iSLIP	$N + 3 {l o g}_{2} (M) + 4$
	LQF-LQF	$N + M + 4$
SSS	iSLIP	$3 {l o g}_{2} (MN) + 2$
$MN$ ports	LQF	$MN + 2$

Cyclone IV E	iSLIP	LQF
$MN = 8$	17,348 (15%)	22,081 (19%)
$MN = 16$	74,462 (65%)	94,806 (83%)
Stratix IV GX	iSLIP	LQF
$MN = 8$	9,146 (2%)	14,378 (3%)
$MN = 16$	41,292 (10%)	57,970 (14%)
Stratix 10 GX	iSLIP	LQF
$MN = 8$	6,659 ( $< 1 %$ )	9,517 ( $< 1 %$ )
$MN = 16$	46,700 (5%)	46,960 (5%)

Cyclone IV E	iSLIP-iSLIP	iSLIP-LQF	LQF-iSLIP	LQF-LQF
$M = 2$ $N = 4$	17,590	17,868	20,215	20,630
$M = 2$ $N = 4$	(15%)	(16%)	(18%)	(18%)
$M = 4$ $N = 2$	17,712	19,512	18,361	20,257
$M = 4$ $N = 2$	(15%)	(17%)	(16%)	(18%)
$M = 4$ $N = 4$	60,628	65,574	65,761	69,781
$M = 4$ $N = 4$	(53%)	(57%)	(57%)	(61%)
Stratix IV GX	iSLIP-iSLIP	iSLIP-LQF	LQF-iSLIP	LQF-LQF
$M = 2$ $N = 4$	10,042	10,140	10,772	10,869
$M = 2$ $N = 4$	(2%)	(2%)	(3%)	(3%)
$M = 4$ $N = 2$	10,862	11,036	10,972	11,136
$M = 4$ $N = 2$	(3%)	(3%)	(3%)	(3%)
$M = 4$ $N = 4$	32,264	32,608	33,638	34,063
$M = 4$ $N = 4$	(8%)	(8%)	(8%)	(8%)
$M = 4$ $N = 8$	82,271	90,537	111,812	114,748
$M = 4$ $N = 8$	(20%)	(22%)	(28%)	(28%)
$M = 8$ $N = 4$	76,573	108,376	84,716	111,812
$M = 8$ $N = 4$	(19%)	(27%)	(21%)	(28%)
Stratix 10 GX	iSLIP-iSLIP	iSLIP-LQF	LQF-iSLIP	LQF-LQF
$M = 2$ $N = 4$	6,910	6,995	7,832	7,927
$M = 2$ $N = 4$	( $< 1 %$ )	( $< 1 %$ )	( $< 1 %$ )	( $< 1 %$ )
$M = 4$ $N = 2$	7,036	7,618	7,156	7,699
$M = 4$ $N = 2$	( $< 1 %$ )	( $< 1 %$ )	( $< 1 %$ )	( $< 1 %$ )
$M = 4$ $N = 4$	23,475	24,365	24,980	26,982
$M = 4$ $N = 4$	(3%)	(3%)	(3%)	(3%)
$M = 4$ $N = 8$	90,482	90,799	98,851	102,605
$M = 4$ $N = 8$	(10%)	(10%)	(11%)	(11%)
$M = 8$ $N = 4$	88,307	95,548	89,269	100,582
$M = 8$ $N = 4$	(10%)	(10%)	(10%)	(11%)
$M = 8$ $N = 8$	315,714	330,148	330,211	357,634
$M = 8$ $N = 8$	(34%)	(35%)	(35%)	(38%)

	Size	Memory (bits)
TSS $M$ cards, $N$ ports per card	$M = 2$ $N = 4$	327,680
	$M = 4$ $N = 2$	327,680
	$M = 4$ $N = 4$	1,310,720
	$M = 4$ $N = 8$	5,242,880
	$M = 8$ $N = 4$	5,242,880
	$M = 8$ $N = 8$	14,680,064
SSS $MN$ ports	$MN = 8$	327,680
SSS $MN$ ports	$MN = 16$	1,310,720

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Journal of Optical Communications and Networking