Abstract
This paper describes a low-power, low-latency, burst-mode DC-coupled receiver for photonic switch networks. The receiver includes a transimpedance amplifier (TIA) followed by a three-stage differential amplifier. For burst-mode operation, DC and timing recovery loops work concurrently in the proposed architecture to achieve 5.8 ns lock time. The DC recovery loop employs a successive approximation algorithm to recover signal-dependent offset that takes only six cycles of C8 (1/8th of data rate) clock. The timing recovery uses a quarter-rate injection scheme that is immune to duty cycle distortion. The recovered clock jitter is 10 ps p-p for operation. The receiver consumes only 33 mW while operating at , and less than 2 mW (leakage power and bias circuit) during idle time. The completely inductor-less receiver occupies a area in 0.13 μm technology.
© 2018 Optical Society of America
Full Article | PDF ArticleMore Like This
Xin Yin, Xing-Zhi Qiu, Jan Gillis, Jasmien Put, Jochen Verbrugghe, Johan Bauwelinck, Jan Vandewege, Heinz Krimmel, Dora van Veen, Peter Vetter, and Frank Chang
J. Opt. Commun. Netw. 4(11) B68-B76 (2012)
Stefano Porto, Cleitus Antony, Anil Jain, Denis Kelly, Daniel Carey, Giuseppe Talli, Peter Ossieur, and Paul D. Townsend
J. Opt. Commun. Netw. 7(1) A118-A125 (2015)
Yisong Zhao, Xuwei Xue, Bingli Guo, Changsheng Yang, Ran Wen, Shikui Shen, Buzheng Wei, Daohang Dang, Yuanzhi Guo, Xiongfei Ren, Bin Chen, and Shanguo Huang
J. Opt. Commun. Netw. 16(3) 294-303 (2024)