Abstract
This work optimizes dynamic characteristic of a new amorphous
silicon gate (ASG) driver circuit using multi-objective evolutionary
algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit
simulator running on the platform of unified optimization framework
(UOF). The ASG driver circuit consisting of 17 a-Si:H TFTs is optimized
for the given specifications of the fall time
${<} 3$
$\mu$
s and the ripple voltage
${<} -$
9 V while simultaneously
minimizing the total layout area. More than 50% reductions on the
fall time of the ASG driver circuit have been achieved by using the
optimization methodology together with a novel three-level clock driving
technique. The measured results of the fabricated sample using the
optimized parameters confirm the practicability of reported MOEA methodology.
© 2015 IEEE
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