Abstract
Grain growth from molten silicon during micro-thermal-plasma-jet (
$\mu$
-TPJ) irradiation
has been controlled by applying amorphous-silicon (a-Si) strips. The grain
boundaries (GBs) in strip pattern with the width of
${{1}}~\mu{{m}}$
are significantly
reduced compared with the case without strip pattern. In strip pattern, random
GBs were almost excluded and most of the strips consist of
$\sum 3$
coincidence site lattices (CSLs)
GBs or in some cases single grains. TFTs with strip pattern showed threshold
voltage
$({V}_{\rm th})$
, field effect mobility
$(\mu_{\rm
FE})$
and sub-threshold swing value (S) of
${{1.8}} \pm {{0.10}}~{{V}}$
,
${{303}} \pm {{24}}~{{cm}}^{2}/{{V}}\cdot{{s}}$
and
${{240}}\pm
{{17}}~{{mV/dec}}$
, respectively. In the case of
P-type TFTs, they were
$-{{1.8}}\pm
{{0.22}}~{{V}}$
,
${{98}}\pm {{7}}~{{cm}}^{2}/{{V}}\cdot{{s}}$
,
${{285}}
\pm {{17}}~{{mV/dec}}$
, respectively. TFTs fabricated
with the proposed pattern showed high performance and the variability reduced
to
$1/3$
compared
with the case without strip pattern. These characteristics and small variation
with proposed patterns enabled us to operate CMOS circuits. The 8-bits shift
register fabricated with proposed pattern was operated at a supply voltage
of 5 V clock frequency of 4 MHz.
© 2014 IEEE
PDF Article
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