Performance analysis of self-electro-optic-effect-device-based (SEED-based) smart-pixel arrays used in data sorting

M. P. Y. Desmulliez; B. S. Wherrett; A. J. Waddie; J. F. Snowdon; J. A. B. Dines

doi:10.1364/AO.35.006397

Performance analysis of self-electro-optic-effect-device-based (SEED-based) smart-pixel arrays used in data sorting

M. P. Y. Desmulliez, B. S. Wherrett, A. J. Waddie, J. F. Snowdon, and J. A. B. Dines

Applied Optics
Vol. 35,
Issue 32,
pp. 6397-6416
(1996)
•https://doi.org/10.1364/AO.35.006397

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M. P. Y. Desmulliez, B. S. Wherrett, A. J. Waddie, J. F. Snowdon, and J. A. B. Dines, "Performance analysis of self-electro-optic-effect-device-based (SEED-based) smart-pixel arrays used in data sorting," Appl. Opt. 35, 6397-6416 (1996)

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History
- Original Manuscript: February 20, 1996
- Revised Manuscript: June 3, 1996
- Published: November 10, 1996

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Abstract

The performance factors associated with self-electro-optic-effect-device- (SEED-) based smart-pixel arrays are analyzed in terms of semiconductor technology and pixel complexity. The sorting task is chosen as a practical example. Complementary metal-oxide semiconductor (CMOS)–SEED 2 × 2 self-routing nodes operated with quasi-cw-mode lasers are shown to provide the maximum processing power and on-or off-chip communication rate. The need for new front-end amplifiers for the smart-pixel technology is emphasized.

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Definition	Symbol	Value
Applied voltage	V ₀	8 V
Voltage threshold of minimum responsivity	V_m	4 V
Voltage threshold for current	−V_t	−1 V
Maximum responsivity voltage	V_p	1 V
Peak responsivity	S_p	0.5 A/W
Minimum responsivity	S_m	0.3 A/W
Mean responsivity	$\bar{S}$	0.5 A/W
Logic-0 reflectivity at λ₀	R_p	0.125
Logic-1 reflectivity at λ₀	R_m	0.375
Logic-0 reflectivity at λ₁	R_p ¹	0.10
Logic-1 reflectivity at λ₁	R_m ¹	0.60
Saturation irradiance	I _sat	3 kW/cm²
S-SEED window area	A	5 × 10 μm²
L-SEED window area	A	5 × 5 μm²
CMOS- and FET-SEED window area	A	10 × 10 μm²
Maximum input-voltage swing	ΔV _in	0.25 V
Logic-voltage swing	ΔV _log	1 V
Word length	L	8
Transconductance	g_m	10⁻³ S
Input-gate capacitance	C _inp	60 fF
Bond-pad capacitance	C _pad	200 fF
First electronic stage output capacitance	C _out	120 fF
Detector capacitance per area	C _cap	200 aF/μm²

	S-SEED	CMOS-SEED	FET-SEED
Throughput (Mops)	3.4	140	4.8
Clock period (ns)	46	14.3	3.3
Optical pulse duration (ns)	23	4.3	0.13
Channel number	32 × 64	32 × 64	8 × 8
Active chip area (cm²)	0.02	0.8	0.6
Number of logic chips required	8	1	1
Number of clock periods	13,244	1000	64,480
Time to sort a single 32² data set (μs)	609	14.3	213
Laser-source power per chip (W)	1	1	1
Maximum power dissipation on chip (W)	0.16	2.5	5.4
Communication Rate (pin-Hz)	4.5 × 10¹⁰	2.9 × 10¹¹	3.9 × 10¹⁰
Data rate (MHz)	22	70	303
Optical pin number (input–output)	2048	4096	128
On-chip gate (switches per second)	4.5 × 10¹⁰	2.4 × 10¹³	2.3 × 10¹²

Definition	Symbol	Value
Applied voltage	V ₀	8 V
Voltage threshold of minimum responsivity	V_m	4 V
Voltage threshold for current	−V_t	−1 V
Maximum responsivity voltage	V_p	1 V
Peak responsivity	S_p	0.5 A/W
Minimum responsivity	S_m	0.3 A/W
Mean responsivity	$\bar{S}$	0.5 A/W
Logic-0 reflectivity at λ₀	R_p	0.125
Logic-1 reflectivity at λ₀	R_m	0.375
Logic-0 reflectivity at λ₁	R_p ¹	0.10
Logic-1 reflectivity at λ₁	R_m ¹	0.60
Saturation irradiance	I _sat	3 kW/cm²
S-SEED window area	A	5 × 10 μm²
L-SEED window area	A	5 × 5 μm²
CMOS- and FET-SEED window area	A	10 × 10 μm²
Maximum input-voltage swing	ΔV _in	0.25 V
Logic-voltage swing	ΔV _log	1 V
Word length	L	8
Transconductance	g_m	10⁻³ S
Input-gate capacitance	C _inp	60 fF
Bond-pad capacitance	C _pad	200 fF
First electronic stage output capacitance	C _out	120 fF
Detector capacitance per area	C _cap	200 aF/μm²

	S-SEED	CMOS-SEED	FET-SEED
Throughput (Mops)	3.4	140	4.8
Clock period (ns)	46	14.3	3.3
Optical pulse duration (ns)	23	4.3	0.13
Channel number	32 × 64	32 × 64	8 × 8
Active chip area (cm²)	0.02	0.8	0.6
Number of logic chips required	8	1	1
Number of clock periods	13,244	1000	64,480
Time to sort a single 32² data set (μs)	609	14.3	213
Laser-source power per chip (W)	1	1	1
Maximum power dissipation on chip (W)	0.16	2.5	5.4
Communication Rate (pin-Hz)	4.5 × 10¹⁰	2.9 × 10¹¹	3.9 × 10¹⁰
Data rate (MHz)	22	70	303
Optical pin number (input–output)	2048	4096	128
On-chip gate (switches per second)	4.5 × 10¹⁰	2.4 × 10¹³	2.3 × 10¹²

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