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Conferences > OFC > 2020 > W3G > W3G.4

A 0.57-mW/Gbps, 2ch x 53-Gbps Low-Power PAM4 Transmitter Front-End Flip-Chip-Bonded 1.3-μm LD-Array-on-Si

Toshiki Kishi, Munehiko Nagatani, Shigeru Kanazawa, Kota Shikama, Takuro Fujii, Hidetaka Nishi, Hiroshi Yamazaki, Norio Sato, Hideyuki Nosaka, and Shinji Matsuo

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Abstract

A low-power 2-channel PAM4 transmitter front-end consisting of 65-nm CMOS PAM4 shunt LD drivers and flip-chip-bonded 1.3-μm LD-array-on-Si achieves simultaneous 2ch × 53-Gps PAM4 transmission over 2-km-long SSMF with power efficiency of 0.57 mW/Gbps.

© 2020 The Author(s)

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