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Conferences > OFC > 2020 > Th2A > Th2A.38

ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers

Christoffer Fougstedt, Oscar Gustafsson, Cheolyong Bae, Erik Börjeson, and Per Larsson-Edefors

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Abstract

We perform exploratory ASIC design of key DSP and FEC units for 400-Gbit/s coherent data-center interconnect receivers. In 22-nm CMOS, the considered units together dissipate 5 W, suggesting implementation feasibility in power-constrained form factors.

© 2020 The Author(s)

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