Ultralow Latency Computation based on Integrated Nanophotonics

Masaya Notomi; Masaya Notomi; Kengo Nozaki; Kengo Nozaki; Shota Kita; Shota Kita; Akihiko Shinya; Akihiko Shinya; Tohru Ishihara; Koji Inoue

JSAP-OSA Joint Symposia 2018
(Optica Publishing Group, 2018),
paper 21p_211B_1

Ultralow Latency Computation based on Integrated Nanophotonics

Masaya Notomi, Kengo Nozaki, Shota Kita, Akihiko Shinya, Tohru Ishihara, and Koji Inoue

JSAP-OSA Joint Symposia 2018

Nagoya Japan
18–21 September 2018
ISBN: 978-4-86348-694-2

From the session
Photonics Devices, Photonic Integrated Circuit and Silicon Phonics (4.2)

Open Access

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M. Notomi, K. Nozaki, S. Kita, A. Shinya, T. Ishihara, and K. Inoue, "Ultralow Latency Computation based on Integrated Nanophotonics," in JSAP-OSA Joint Symposia 2018, (Optica Publishing Group, 2018), paper 21p_211B_1.

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Abstract

Moore’s law for CMOS computers is still continuing, but its near-future saturation is now being discussed.

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