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Conferences > CLEO_SI > 2018 > SF1A > SF1A.2

Silicon Linear Optical Logic Gates for Low-Latency Computing

Shota Kita, Kengo Nozaki, Kenta Takata, Akihiko Shinya, and Masaya Notomi

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Abstract

We demonstrate 3 μm-long linear optical logic gates with a bias input. The binary contrasts of AND/NOR operations can be 9.5 dB without signal attenuation. This may open up a new boundary for ultralow-latency computing.

© 2018 The Author(s)

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