Abstract

One of the important advantages of Si photonics devices is their compactness, which derives from the high refractive index of Si [1]. However, this compactness also causes a problem for a specific application. For example, let us consider an attachment of a 40ch fibre array to Si photonics devices. A 40ch fibre array is wider than 10 mm (or 5 mm), because the typical pitch of standard optical fibres is fixed at 250 μm (or 127μm). Therefore, at least one side of a Si photonics chip will be wider than a 40ch fibre array. This makes the Si photonics footprint larger and reduces the number of chips that we can layout on one wafer.

© 2009 IEEE