Expand this Topic clickable element to expand a topic
Skip to content
Optica Publishing Group
  • Conference on Lasers and Electro-Optics/Pacific Rim 2009
  • (Optica Publishing Group, 2009),
  • paper ThH4_2

On the Feasibility of Reconfigurable Photonic Network on Chip

Not Accessible

Your library or personal account may give you access

Abstract

Reconfigurable photonic network for multi-processor on chip communication is considered. With different application pattern, this architecture can significantly improve the latency performance of multi-processor chips.

© 2009 IEEE

PDF Article
More Like This
Ultra-low Latency Reconfigurable Photonic Network on Chip Architecture Based on Application Pattern

Yu Gao, Yaohui Jin, Zhijuan Chang, and Weisheng Hu
OTuI4 Optical Fiber Communication Conference (OFC) 2009

Deflection Routing in Multi-Channel Photonic Network on Chip Architecture

Jianxiong Tang, Yaohui Jin, and Zhijuan Chang
ThD3 Asia Communications and Photonics Conference and Exhibition (ACP) 2009

Optical Circuit Switching Enabled Reconfigurable HPC Network for Traffic Pattern

Shang Yu, Bingli Guo, Wenzhe Li, Yu Zhou, Xin Li, and Shanguo Huang
W4I.5 Optical Fiber Communication Conference (OFC) 2018

Select as filters


Select Topics Cancel
© Copyright 2024 | Optica Publishing Group. All rights reserved, including rights for text and data mining and training of artificial technologies or similar technologies.